From 80c63c0da69eeb61f1886c384c30a79044c86573 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Fri, 2 Jun 2017 15:29:30 -0700
Subject: [PATCH] rocket: include hartid in cache master names

---
 src/main/scala/groundtest/Tile.scala   |  2 +-
 src/main/scala/rocket/DCache.scala     |  2 +-
 src/main/scala/rocket/HellaCache.scala | 17 +++++++++--------
 src/main/scala/rocket/NBDcache.scala   |  2 +-
 4 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/src/main/scala/groundtest/Tile.scala b/src/main/scala/groundtest/Tile.scala
index 7503533c..61c83c35 100644
--- a/src/main/scala/groundtest/Tile.scala
+++ b/src/main/scala/groundtest/Tile.scala
@@ -69,7 +69,7 @@ abstract class GroundTest(implicit val p: Parameters) extends Module
 class GroundTestTile(implicit p: Parameters) extends LazyModule
     with HasGroundTestParameters {
   val slave = None
-  val dcacheOpt = tileParams.dcache.map { dc => HellaCache(dc.nMSHRs == 0) }
+  val dcacheOpt = tileParams.dcache.map { dc => HellaCache(0, dc.nMSHRs == 0) }
   val ucLegacy = LazyModule(new TLLegacy)
 
    val masterNode = TLOutputNode()
diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala
index a0800937..1b81ec5f 100644
--- a/src/main/scala/rocket/DCache.scala
+++ b/src/main/scala/rocket/DCache.scala
@@ -39,7 +39,7 @@ class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   }
 }
 
-class DCache(val scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) extends HellaCache()(p) {
+class DCache(hartid: Int, val scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) extends HellaCache(hartid)(p) {
   override lazy val module = new DCacheModule(this) 
 }
 
diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala
index cab7318e..f1c1fd45 100644
--- a/src/main/scala/rocket/HellaCache.scala
+++ b/src/main/scala/rocket/HellaCache.scala
@@ -147,23 +147,23 @@ class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) {
 
 /** Base classes for Diplomatic TL2 HellaCaches */
 
-abstract class HellaCache(implicit p: Parameters) extends LazyModule {
+abstract class HellaCache(hartid: Int)(implicit p: Parameters) extends LazyModule {
   private val cfg = p(TileKey).dcache.get
   val firstMMIO = max(1, cfg.nMSHRs)
 
   val node = TLClientNode(Seq(TLClientPortParameters(
     clients = cfg.scratch.map { _ => Seq(
       TLClientParameters(
-        name          = s"Core xx DCache MMIO",
+        name          = s"Core ${hartid} DCache MMIO",
         sourceId      = IdRange(0, cfg.nMMIOs),
         requestFifo   = true))
     } getOrElse { Seq(
       TLClientParameters(
-        name          = s"Core xx DCache MMIO",
+        name          = s"Core ${hartid} DCache",
          sourceId      = IdRange(0, firstMMIO),
          supportsProbe = TransferSizes(1, cfg.blockBytes)),
       TLClientParameters(
-        name          = s"Core xx DCache",
+        name          = s"Core ${hartid} DCache MMIO",
         sourceId      = IdRange(firstMMIO, firstMMIO+cfg.nMMIOs),
         requestFifo   = true))
     },
@@ -189,9 +189,9 @@ class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
 }
 
 object HellaCache {
-  def apply(blocking: Boolean, scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) = {
-    if (blocking) LazyModule(new DCache(scratch))
-    else LazyModule(new NonBlockingDCache)
+  def apply(hartid: Int, blocking: Boolean, scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) = {
+    if (blocking) LazyModule(new DCache(hartid, scratch))
+    else LazyModule(new NonBlockingDCache(hartid))
   }
 }
 
@@ -201,8 +201,9 @@ trait HasHellaCache extends HasTileLinkMasterPort with HasTileParameters {
   val module: HasHellaCacheModule
   implicit val p: Parameters
   def findScratchpadFromICache: Option[AddressSet]
+  val hartid: Int
   var nDCachePorts = 0
-  val dcache = HellaCache(tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _)
+  val dcache = HellaCache(hartid, tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _)
   tileBus.node := dcache.node
 }
 
diff --git a/src/main/scala/rocket/NBDcache.scala b/src/main/scala/rocket/NBDcache.scala
index 0e7422ca..cfda10f4 100644
--- a/src/main/scala/rocket/NBDcache.scala
+++ b/src/main/scala/rocket/NBDcache.scala
@@ -660,7 +660,7 @@ class DataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   io.write.ready := Bool(true)
 }
 
-class NonBlockingDCache(implicit p: Parameters) extends HellaCache()(p) {
+class NonBlockingDCache(hartid: Int)(implicit p: Parameters) extends HellaCache(hartid)(p) {
   override lazy val module = new NonBlockingDCacheModule(this) 
 }