riscv/rocket-chip
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rocket: include hartid in cache master names

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This commit is contained in:
Wesley W. Terpstra
2017-06-02 15:29:30 -07:00
parent d25ad10592
commit 80c63c0da6
4 changed files with 12 additions and 11 deletions
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2
src/main/scala/groundtest/Tile.scala
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@ -69,7 +69,7 @@ abstract class GroundTest(implicit val p: Parameters) extends Module
class GroundTestTile(implicit p: Parameters) extends LazyModule
with HasGroundTestParameters {
val slave = None
val dcacheOpt = tileParams.dcache.map { dc => HellaCache(dc.nMSHRs == 0) }
val dcacheOpt = tileParams.dcache.map { dc => HellaCache(0, dc.nMSHRs == 0) }
val ucLegacy = LazyModule(new TLLegacy)
val masterNode = TLOutputNode()