From 7d94074b05a91403dca88fb2f4195174d3f69f29 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 6 Aug 2017 17:36:53 -0700 Subject: [PATCH 1/2] Remove one gate from D$ ECC check The D$ corrects via writeback, so which word the error was in doesn't matter, as the entire line is corrected. --- src/main/scala/rocket/DCache.scala | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index e83796ea..85073c64 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -232,7 +232,10 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val (s2_hit, s2_grow_param, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd) val s2_data_decoded = decodeData(s2_data) val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) - val s2_data_error = needsRead(s2_req) && (s2_data_decoded.map(_.error).grouped(wordBits/eccBits).map(_.reduce(_||_)).toSeq)(s2_word_idx) + val s2_data_error = { + val word_errors = s2_data_decoded.map(_.error).grouped(wordBits/eccBits).map(_.reduce(_||_)).toSeq + needsRead(s2_req) && (if (usingDataScratchpad) word_errors(s2_word_idx) else word_errors.reduce(_||_)) + } val s2_data_corrected = (s2_data_decoded.map(_.corrected): Seq[UInt]).asUInt val s2_data_uncorrected = (s2_data_decoded.map(_.uncorrected): Seq[UInt]).asUInt val s2_valid_hit_pre_data_ecc = s2_valid_masked && s2_readwrite && !s2_meta_error && s2_hit From 658e36f98b4f40b407c30f36d9cf47cc71a2e267 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 6 Aug 2017 17:38:51 -0700 Subject: [PATCH 2/2] Reduce fanout on frontend io.cpu.req.valid signal --- src/main/scala/rocket/Frontend.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala index 8e545708..b4088bfe 100644 --- a/src/main/scala/rocket/Frontend.scala +++ b/src/main/scala/rocket/Frontend.scala @@ -119,8 +119,8 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) val s2_redirect = Wire(init = io.cpu.req.valid) s2_valid := false - when (!s2_replay && !s2_redirect) { - s2_valid := true + when (!s2_replay) { + s2_valid := !s2_redirect s2_pc := s1_pc s2_speculative := s1_speculative s2_tlb_resp := tlb.io.resp