update to new scala/chisel/Mem

rocket/src/main/scala/dpath_util.scala

@@ -252,9 +252,7 @@ class rocketDpathRegfile extends Component
   override val io = new ioRegfile();
 
   val regfile = Mem(32){ Bits(width=64) }
-  regfile.setReadLatency(0);
+  when (io.w0.en) { regfile(io.w0.addr) := io.w0.data }
-  regfile.setTarget('inst);
-  regfile.write(io.w0.addr, io.w0.data, io.w0.en);
   io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr));
   io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr));
 }

rocket/src/main/scala/dtlb.scala

@@ -74,7 +74,8 @@ class rocketDTLB(entries: Int) extends Component
   val bad_va = r_cpu_req_vpn(VPN_BITS) != r_cpu_req_vpn(VPN_BITS-1);
 
   val tag_cam = new rocketCAM(entries, ASID_BITS+VPN_BITS);
-  val tag_ram = Mem(entries, io.ptw.resp_val, r_refill_waddr.toUFix, io.ptw.resp_ppn);
+  val tag_ram = Mem(entries) { io.ptw.resp_ppn.clone }
+  when (io.ptw.resp_val) { tag_ram(r_refill_waddr) := io.ptw.resp_ppn }
   
   val lookup_tag = Cat(r_cpu_req_asid, r_cpu_req_vpn);
   tag_cam.io.clear      := io.invalidate;

rocket/src/main/scala/fpu.scala

@@ -464,9 +464,8 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
   val fsr_exc = Reg() { Bits(width = 5) }
 
   // regfile
-  val regfile = Mem(32, load_wb, load_wb_tag, load_wb_data_recoded);
+  val regfile = Mem(32) { Bits(width = 65) }
-  regfile.setReadLatency(0);
+  when (load_wb) { regfile(load_wb_tag) := load_wb_data_recoded }
-  regfile.setTarget('inst);
 
   val ex_rs1 = regfile.read(ex_reg_inst(26,22))
   val ex_rs2 = regfile.read(ex_reg_inst(21,17))
@@ -591,7 +590,7 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
              Mux(wsrc === UFix(2), fastpipe.io.exc_d,
              fastpipe.io.exc_s)))
   val waddr = winfo(0).toUFix >> UFix(2)
-  regfile.write(waddr(4,0), wdata, wen(0))
+  when (wen(0)) { regfile(waddr(4,0)) := wdata }
 
   when (wb_reg_valid && wb_ctrl.toint || wen(0)) {
     fsr_exc := fsr_exc |

rocket/src/main/scala/icache.scala

@@ -97,10 +97,10 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten
   for (i <- 0 until assoc)
   {
     val repl_me = (repl_way === UFix(i))
-    val tag_array = Mem(sets){ r_cpu_miss_tag }
+    val tag_array = Mem(sets){ Bits(width = tagbits) }
-    tag_array.setReadLatency(1);
+    val tag_rdata = Reg() { Bits(width = tagbits) }
-    tag_array.setTarget('inst);
+    when (tag_we && repl_me) { tag_array(tag_addr) := r_cpu_miss_tag }
-    val tag_rdata = tag_array.rw(tag_addr, r_cpu_miss_tag, tag_we && repl_me);
+    .otherwise { tag_rdata := tag_array(tag_addr) }
 
     // valid bit array
     val vb_array = Reg(resetVal = Bits(0, sets));
@@ -115,10 +115,10 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten
     val hit = valid && (tag_rdata === r_cpu_hit_addr(tagmsb,taglsb))
     
     // data array
-    val data_array = Mem(sets*REFILL_CYCLES){ io.mem.xact_rep.bits.data }
+    val data_array = Mem(sets*REFILL_CYCLES){ io.mem.xact_rep.bits.data.clone }
-    data_array.setReadLatency(1);
+    val data_out = Reg(){ io.mem.xact_rep.bits.data.clone }
-    data_array.setTarget('inst);
+    when (io.mem.xact_rep.valid && repl_me) { data_array(data_addr) := io.mem.xact_rep.bits.data }
-    val data_out = data_array.rw(data_addr, io.mem.xact_rep.bits.data, io.mem.xact_rep.valid && repl_me)
+    .otherwise { data_out := data_array(data_addr) }
 
     data_mux.io.sel(i) := hit
     data_mux.io.in(i) := (data_out >> word_shift)(databits-1,0);

rocket/src/main/scala/itlb.scala

@@ -21,23 +21,24 @@ class ioCAM(entries: Int, addr_bits: Int, tag_bits: Int) extends Bundle {
 class rocketCAM(entries: Int, tag_bits: Int) extends Component {
   val addr_bits = ceil(log(entries)/log(2)).toInt;
   val io = new ioCAM(entries, addr_bits, tag_bits);
-  val cam_tags = Mem(entries, io.write, io.write_addr, io.write_tag);
+  val cam_tags = Vec(entries) { Reg() { Bits(width = tag_bits) } }
   val mux = (new Mux1H(entries)) { Bits(width = addr_bits) }
 
   val vb_array = Reg(resetVal = Bits(0, entries));
+  when (io.write) {
+    vb_array := vb_array.bitSet(io.write_addr, Bool(true));
+    cam_tags(io.write_addr) := io.write_tag
+  }
   when (io.clear) {
     vb_array := Bits(0, entries);
   }
   .elsewhen (io.clear_hit) {
     vb_array := vb_array & ~mux.io.sel.toBits
   }
-  .elsewhen (io.write) {
-    vb_array := vb_array.bitSet(io.write_addr, Bool(true));
-  }
   
   var l_hit = Bool(false)
   for (i <- 0 to entries-1) {
-    val my_hit = vb_array(UFix(i)).toBool && (cam_tags(UFix(i)) === io.tag)
+    val my_hit = vb_array(UFix(i)).toBool && (cam_tags(i) === io.tag)
     l_hit = l_hit || my_hit
     mux.io.in(i) := Bits(i)
     mux.io.sel(i) := my_hit
@@ -136,7 +137,8 @@ class rocketITLB(entries: Int) extends Component
   val bad_va = r_cpu_req_vpn(VPN_BITS) != r_cpu_req_vpn(VPN_BITS-1);
   
   val tag_cam = new rocketCAM(entries, ASID_BITS+VPN_BITS);
-  val tag_ram = Mem(entries, io.ptw.resp_val, r_refill_waddr.toUFix, io.ptw.resp_ppn);
+  val tag_ram = Mem(entries) { io.ptw.resp_ppn.clone }
+  when (io.ptw.resp_val) { tag_ram(r_refill_waddr) := io.ptw.resp_ppn }
   
   val lookup_tag = Cat(r_cpu_req_asid, r_cpu_req_vpn);
   tag_cam.io.clear      := io.cpu.invalidate;

rocket/src/main/scala/nbdcache.scala

@@ -321,9 +321,8 @@ class MSHRFile(co: CoherencePolicy) extends Component {
   val sdq_rdy = !sdq_val.andR
   val (req_read, req_write) = cpuCmdToRW(io.req.bits.cmd)
   val sdq_enq = io.req.valid && io.req.ready && req_write
-  val sdq = Mem(NSDQ, sdq_enq, sdq_alloc_id, io.req.bits.data)
+  val sdq = Mem(NSDQ) { io.req.bits.data.clone }
-  sdq.setReadLatency(1);
+  when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data }
-  sdq.setTarget('inst)
 
   val tag_mux = (new Mux1H(NMSHR)){ Bits(width = TAG_BITS) }
   val wb_probe_mux = (new Mux1H(NMSHR)) { new WritebackReq }
@@ -406,7 +405,9 @@ class MSHRFile(co: CoherencePolicy) extends Component {
   val sdq_free = replay.valid && replay.ready && replay_write
   sdq_val := sdq_val & ~((UFix(1) << replay.bits.sdq_id) & Fill(sdq_free, NSDQ)) | 
              PriorityEncoderOH(~sdq_val(NSDQ-1,0)) & Fill(NSDQ, sdq_enq && io.req.bits.tag_miss)
-  io.data_req.bits.data := sdq.read(Mux(replay.valid && !replay.ready, replay.bits.sdq_id, replay_arb.io.out.bits.sdq_id))
+  val sdq_rdata = Reg() { io.req.bits.data.clone }
+  sdq_rdata := sdq(Mux(replay.valid && !replay.ready, replay.bits.sdq_id, replay_arb.io.out.bits.sdq_id))
+  io.data_req.bits.data := sdq_rdata
 
   io.cpu_resp_val := Reg(replay.valid && replay.ready && replay_read, resetVal = Bool(false))
   io.cpu_resp_tag := Reg(replay.bits.cpu_tag)
@@ -602,18 +603,23 @@ class MetaDataArray(lines: Int) extends Component {
   }
 
   val permissions_array = Mem(lines){ UFix(width = 2) }
-  permissions_array.write(io.state_req.bits.idx, io.state_req.bits.data.state, io.state_req.valid && io.state_req.bits.rw)
-  permissions_array.write(io.req.bits.idx, io.req.bits.data.state, io.req.valid && io.req.bits.rw)
   val raddr = Reg() { Bits() }
-  when (io.req.valid && !io.req.bits.rw) { raddr := io.req.bits.idx }
+  when (io.state_req.valid && io.state_req.bits.rw) {
-  val permissions_rdata1 = permissions_array.read(raddr)
+    permissions_array(io.state_req.bits.idx) := io.state_req.bits.data.state
+  }
+  when (io.req.valid) {
+    when (io.req.bits.rw) { permissions_array(io.req.bits.idx) := io.req.bits.data.state }
+    .otherwise { raddr := io.req.bits.idx }
+  }
 
   val tag_array = Mem(lines){ Bits(width=TAG_BITS) }
-  tag_array.setReadLatency(1);
+  val tag_rdata = Reg() { Bits() }
-  tag_array.setTarget('inst)
+  when (io.req.valid) {
-  val tag_rdata = tag_array.rw(io.req.bits.idx, io.req.bits.data.tag, io.req.valid && io.req.bits.rw, cs = io.req.valid)
+    when (io.req.bits.rw) { tag_array(io.req.bits.idx) := io.req.bits.data.tag }
+    .otherwise { tag_rdata := tag_array(io.req.bits.idx) }
+  }
 
-  io.resp.state := permissions_rdata1.toUFix
+  io.resp.state := permissions_array(raddr)
   io.resp.tag   := tag_rdata
   io.req.ready  := Bool(true)
 }
@@ -652,12 +658,15 @@ class DataArray(lines: Int) extends Component {
   }
 
   val wmask = FillInterleaved(8, io.req.bits.wmask)
+  val addr = Cat(io.req.bits.idx, io.req.bits.offset)
+  val rdata = Reg() { Bits() }
 
   val array = Mem(lines*REFILL_CYCLES){ Bits(width=MEM_DATA_BITS) }
-  array.setReadLatency(1);
+  when (io.req.valid) {
-  array.setTarget('inst)
+    when (io.req.bits.rw) { array.write(addr, io.req.bits.data, wmask) }
-  val addr = Cat(io.req.bits.idx, io.req.bits.offset)
+    .otherwise { rdata := array(addr) }
-  val rdata = array.rw(addr, io.req.bits.data, io.req.valid && io.req.bits.rw, wmask, cs = io.req.valid)
+  }
+
   io.resp := rdata
   io.req.ready := Bool(true)
 }

rocket/src/main/scala/queues.scala

@@ -50,9 +50,12 @@ class queue[T <: Data](entries: Int, pipe: Boolean = false, flushable: Boolean =
     }
   }
 
+  val ram = Vec(entries) { Reg() { data } }
+  when (do_enq) { ram(enq_ptr) := io.enq.bits }
+
   io.deq.valid :=  maybe_full || enq_ptr != deq_ptr
   io.enq.ready := !maybe_full || enq_ptr != deq_ptr || (if (pipe) io.deq.ready else Bool(false))
-  io.deq.bits <> Mem(entries, do_enq, enq_ptr, io.enq.bits).read(deq_ptr)
+  io.deq.bits <> ram(deq_ptr)
 }
 
 object Queue
@@ -76,8 +79,11 @@ class pipereg[T <: Data]()(data: => T) extends Component
   //  bits := io.enq.bits
   //}
 
+  val reg = Reg() { io.enq.bits.clone }
+  when (io.enq.valid) { reg := io.enq.bits }
+
   io.deq.valid := Reg(io.enq.valid, resetVal = Bool(false))
-  io.deq.bits <> Mem(1, io.enq.valid, UFix(0), io.enq.bits).read(UFix(0))
+  io.deq.bits <> reg
 }
 
 object Pipe

rocket/src/main/scala/top.scala

@@ -3,6 +3,7 @@ package rocket
 import Chisel._
 import Node._;
 import Constants._;
+import collection.mutable._
 
 class ioTop(htif_width: Int) extends Bundle  {
   val debug   = new ioDebug();
@@ -82,28 +83,31 @@ class Top extends Component
 
 object top_main {
   def main(args: Array[String]): Unit = { 
-    val design_args = args.slice(5, 10)
+    val top = args(0)
-    var i = 0
+    val chiselArgs = ArrayBuffer[String]()
-    while (i < design_args.length) {
+
-      val arg = design_args(i)
+    var i = 1
+    while (i < args.length) {
+      val arg = args(i)
       arg match {
         case "--NUM_PVFB" => {
-          hwacha.Constants.NUM_PVFB = design_args(i+1).toInt
+          hwacha.Constants.NUM_PVFB = args(i+1).toInt
           i += 1
         }
         case "--WIDTH_PVFB" => {
-          hwacha.Constants.WIDTH_PVFB = design_args(i+1).toInt
+          hwacha.Constants.WIDTH_PVFB = args(i+1).toInt
-          hwacha.Constants.DEPTH_PVFB = design_args(i+1).toInt
+          hwacha.Constants.DEPTH_PVFB = args(i+1).toInt
           i += 1
         }
         case "--CG" => {
           hwacha.Constants.coarseGrained = true
         }
-        case any => println("UNKNOWN: " + arg)
+        case any => chiselArgs += arg
       }
-      println(arg)
       i += 1
     }
-    chiselMain(args.slice(1,5), () => Class.forName(args(0)).newInstance.asInstanceOf[Component])
+    println(chiselArgs)
+
+    chiselMain(chiselArgs.toArray, () => Class.forName(top).newInstance.asInstanceOf[Component])
   }
 }