riscv/rocket-chip
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update to new scala/chisel/Mem

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This commit is contained in:
Andrew Waterman
2012-06-06 02:47:22 -07:00
parent 7408c9ab69
commit 7f6319047e
8 changed files with 69 additions and 50 deletions
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16
rocket/src/main/scala/icache.scala
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@ -97,10 +97,10 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten
for (i <- 0 until assoc)
{
val repl_me = (repl_way === UFix(i))
val tag_array = Mem(sets){ r_cpu_miss_tag }
tag_array.setReadLatency(1);
tag_array.setTarget('inst);
val tag_rdata = tag_array.rw(tag_addr, r_cpu_miss_tag, tag_we && repl_me);
val tag_array = Mem(sets){ Bits(width = tagbits) }
val tag_rdata = Reg() { Bits(width = tagbits) }
when (tag_we && repl_me) { tag_array(tag_addr) := r_cpu_miss_tag }
.otherwise { tag_rdata := tag_array(tag_addr) }
// valid bit array
val vb_array = Reg(resetVal = Bits(0, sets));
@ -115,10 +115,10 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten
val hit = valid && (tag_rdata === r_cpu_hit_addr(tagmsb,taglsb))
// data array
val data_array = Mem(sets*REFILL_CYCLES){ io.mem.xact_rep.bits.data }
data_array.setReadLatency(1);
data_array.setTarget('inst);
val data_out = data_array.rw(data_addr, io.mem.xact_rep.bits.data, io.mem.xact_rep.valid && repl_me)
val data_array = Mem(sets*REFILL_CYCLES){ io.mem.xact_rep.bits.data.clone }
val data_out = Reg(){ io.mem.xact_rep.bits.data.clone }
when (io.mem.xact_rep.valid && repl_me) { data_array(data_addr) := io.mem.xact_rep.bits.data }
.otherwise { data_out := data_array(data_addr) }
data_mux.io.sel(i) := hit
data_mux.io.in(i) := (data_out >> word_shift)(databits-1,0);