update to new scala/chisel/Mem
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@ -252,9 +252,7 @@ class rocketDpathRegfile extends Component
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override val io = new ioRegfile();
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val regfile = Mem(32){ Bits(width=64) }
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regfile.setReadLatency(0);
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regfile.setTarget('inst);
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regfile.write(io.w0.addr, io.w0.data, io.w0.en);
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when (io.w0.en) { regfile(io.w0.addr) := io.w0.data }
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io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr));
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io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr));
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}
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