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ahb: backport bridge to chisel2

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Closes #47
This commit is contained in:
Wesley W. Terpstra 2016-05-25 12:25:59 -07:00 committed by Andrew Waterman
parent c49cb10c74
commit 7f1792cba3
1 changed files with 1 additions and 1 deletions
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2
uncore/src/main/scala/ahb.scala
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@ -241,7 +241,7 @@ class AHBBusMaster(implicit val p: Parameters) extends Module
val hmastlock = Reg(init = Bool(false)) val hmastlock = Reg(init = Bool(false))
val hwrite = Reg(Bool()) val hwrite = Reg(Bool())
val hburst = Reg(UInt()) val hburst = Reg(UInt())
val hsize = Reg(UInt()) val hsize = Reg(init = UInt(0, width = SZ_HSIZE))
val hprot = Reg(UInt()) val hprot = Reg(UInt())
val hwdata0 = Reg(Bits()) val hwdata0 = Reg(Bits())
val hwdata1 = Reg(Bits()) val hwdata1 = Reg(Bits())