From 7f1792cba3c006ec36df9c22c1bc95328952459f Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 25 May 2016 12:25:59 -0700 Subject: [PATCH] ahb: backport bridge to chisel2 Closes #47 --- uncore/src/main/scala/ahb.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/uncore/src/main/scala/ahb.scala b/uncore/src/main/scala/ahb.scala index 1e1a9455..80442dbe 100644 --- a/uncore/src/main/scala/ahb.scala +++ b/uncore/src/main/scala/ahb.scala @@ -241,7 +241,7 @@ class AHBBusMaster(implicit val p: Parameters) extends Module val hmastlock = Reg(init = Bool(false)) val hwrite = Reg(Bool()) val hburst = Reg(UInt()) - val hsize = Reg(UInt()) + val hsize = Reg(init = UInt(0, width = SZ_HSIZE)) val hprot = Reg(UInt()) val hwdata0 = Reg(Bits()) val hwdata1 = Reg(Bits())