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Merge pull request #899 from freechipsproject/wrapper-dedup

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Stabilize tile wrappers for downstream tools
This commit is contained in:
Henry Cook
2017-07-28 10:52:59 -07:00
committed by GitHub
parent 370cc392e0 b64b87ad07
commit 7eeb9dfd88
3 changed files with 16 additions and 12 deletions
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2
src/main/scala/coreplex/BaseCoreplex.scala
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@ -13,7 +13,7 @@ import freechips.rocketchip.util._
sealed trait CoreplexClockCrossing
case class SynchronousCrossing(params: BufferParams = BufferParams.default) extends CoreplexClockCrossing
case class RationalCrossing(direction: RationalDirection = FastToSlow) extends CoreplexClockCrossing
case class AsynchronousCrossing(depth: Int, sync: Int = 2) extends CoreplexClockCrossing
case class AsynchronousCrossing(depth: Int, sync: Int = 3) extends CoreplexClockCrossing
/** BareCoreplex is the root class for creating a coreplex sub-system */
abstract class BareCoreplex(implicit p: Parameters) extends LazyModule with BindingScope {

3
src/main/scala/coreplex/RocketCoreplex.scala
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@ -57,13 +57,12 @@ trait HasRocketTiles extends HasSystemBus
}
case RationalCrossing(direction) => {
val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra))
val sink = LazyModule(new TLRationalCrossingSink(direction))
val source = LazyModule(new TLRationalCrossingSource)
sbus.fromRationalTiles(direction) :=* wrapper.masterNode
wrapper.slaveNode :*= pbus.toRationalSlaves
wrapper
}
}
wrapper.suggestName("tile") // Try to stabilize this name for downstream tools
// Local Interrupts must be synchronized to the core clock
// before being passed into this module.