diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala
index 7c7be713..157adfb5 100644
--- a/src/main/scala/coreplex/BaseCoreplex.scala
+++ b/src/main/scala/coreplex/BaseCoreplex.scala
@@ -13,7 +13,7 @@ import freechips.rocketchip.util._
 sealed trait CoreplexClockCrossing
 case class SynchronousCrossing(params: BufferParams = BufferParams.default) extends CoreplexClockCrossing
 case class RationalCrossing(direction: RationalDirection = FastToSlow) extends CoreplexClockCrossing
-case class AsynchronousCrossing(depth: Int, sync: Int = 2) extends CoreplexClockCrossing
+case class AsynchronousCrossing(depth: Int, sync: Int = 3) extends CoreplexClockCrossing
 
 /** BareCoreplex is the root class for creating a coreplex sub-system */
 abstract class BareCoreplex(implicit p: Parameters) extends LazyModule with BindingScope {
diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala
index ba0eb6cb..a30cdad5 100644
--- a/src/main/scala/coreplex/RocketCoreplex.scala
+++ b/src/main/scala/coreplex/RocketCoreplex.scala
@@ -57,13 +57,12 @@ trait HasRocketTiles extends HasSystemBus
       }
       case RationalCrossing(direction) => {
         val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra))
-        val sink = LazyModule(new TLRationalCrossingSink(direction))
-        val source = LazyModule(new TLRationalCrossingSource)
         sbus.fromRationalTiles(direction) :=* wrapper.masterNode
         wrapper.slaveNode :*= pbus.toRationalSlaves
         wrapper
       }
     }
+    wrapper.suggestName("tile") // Try to stabilize this name for downstream tools
 
     // Local Interrupts must be synchronized to the core clock
     // before being passed into this module.
diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
index d663d02e..7afcb64d 100644
--- a/src/main/scala/tile/RocketTile.scala
+++ b/src/main/scala/tile/RocketTile.scala
@@ -17,7 +17,8 @@ case class RocketTileParams(
     dcache: Option[DCacheParams] = Some(DCacheParams()),
     rocc: Seq[RoCCParams] = Nil,
     btb: Option[BTBParams] = Some(BTBParams()),
-    dataScratchpadBytes: Int = 0) extends TileParams {
+    dataScratchpadBytes: Int = 0,
+    boundaryBufferParams: BufferParams = BufferParams.flow) extends TileParams {
   require(icache.isDefined)
   require(dcache.isDefined)
 }
@@ -171,7 +172,11 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
   val periphIntNode  = IntInputNode()
   val coreIntNode    = IntInputNode()
   val intXbar = LazyModule(new IntXbar)
+  val masterBuffer = LazyModule(new TLBuffer(rtp.boundaryBufferParams))
+  val slaveBuffer = LazyModule(new TLBuffer(rtp.boundaryBufferParams))
 
+  masterBuffer.node :=* rocket.masterNode
+  rocket.slaveNode connectButDontMonitorSlaves slaveBuffer.node
   rocket.intNode := intXbar.intnode
 
   lazy val module = new LazyModuleImp(this) {
@@ -190,10 +195,10 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
 
 class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
   val masterNode = TLOutputNode()
-  masterNode :=* rocket.masterNode
+  masterNode :=* masterBuffer.node
 
   val slaveNode = new TLInputNode() { override def reverse = true }
-  rocket.slaveNode :*= slaveNode
+  slaveBuffer.node connectButDontMonitorSlaves slaveNode
 
   // Fully async interrupts need synchronizers.
   // Others need no synchronization.
@@ -208,13 +213,13 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters)
 class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
   val masterNode = TLAsyncOutputNode()
   val source = LazyModule(new TLAsyncCrossingSource)
-  source.node :=* rocket.masterNode
+  source.node :=* masterBuffer.node
   masterNode :=* source.node
 
   val slaveNode = new TLAsyncInputNode() { override def reverse = true }
   val sink = LazyModule(new TLAsyncCrossingSink)
-  rocket.slaveNode :*= sink.node
-  sink.node :*= slaveNode
+  slaveBuffer.node connectButDontMonitorSlaves sink.node
+  sink.node connectButDontMonitorSlaves slaveNode
 
   // Fully async interrupts need synchronizers,
   // as do those coming from the periphery clock.
@@ -232,13 +237,13 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters
 class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
   val masterNode = TLRationalOutputNode()
   val source = LazyModule(new TLRationalCrossingSource)
-  source.node :=* rocket.masterNode
+  source.node :=* masterBuffer.node
   masterNode :=* source.node
 
   val slaveNode = new TLRationalInputNode() { override def reverse = true }
   val sink = LazyModule(new TLRationalCrossingSink(SlowToFast))
-  rocket.slaveNode :*= sink.node
-  sink.node :*= slaveNode
+  slaveBuffer.node connectButDontMonitorSlaves sink.node
+  sink.node connectButDontMonitorSlaves slaveNode
 
   // Fully async interrupts need synchronizers.
   // Those coming from periphery clock need a