From 33852ef9652cbfe4537309aeb7d3d48360d3bf2c Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 27 Jul 2017 14:23:03 -0700 Subject: [PATCH 1/5] coreplex: remove superfluous sink and source from wrapper --- src/main/scala/coreplex/RocketCoreplex.scala | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala index 80af5a39..3faa24cd 100644 --- a/src/main/scala/coreplex/RocketCoreplex.scala +++ b/src/main/scala/coreplex/RocketCoreplex.scala @@ -57,8 +57,6 @@ trait HasRocketTiles extends HasSystemBus } case RationalCrossing(direction) => { val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra)) - val sink = LazyModule(new TLRationalCrossingSink(direction)) - val source = LazyModule(new TLRationalCrossingSource) sbus.fromRationalTiles(direction) :=* wrapper.masterNode wrapper.slaveNode :*= pbus.toRationalSlaves wrapper From 9a483af6e8ac54c84d25cafab3221e27d9d33a44 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 27 Jul 2017 15:16:48 -0700 Subject: [PATCH 2/5] coreplex: naming of tile wrappers --- src/main/scala/coreplex/RocketCoreplex.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala index 3faa24cd..bca88589 100644 --- a/src/main/scala/coreplex/RocketCoreplex.scala +++ b/src/main/scala/coreplex/RocketCoreplex.scala @@ -62,6 +62,7 @@ trait HasRocketTiles extends HasSystemBus wrapper } } + wrapper.suggestName("tile") // Try to stabilize this name for downstream tools // Local Interrupts must be synchronized to the core clock // before being passed into this module. From 266ed56e8d7209f57b23d84b5160004f2327d9c0 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 27 Jul 2017 15:28:53 -0700 Subject: [PATCH 3/5] tile: turn off more slave port monitors --- src/main/scala/tile/RocketTile.scala | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index d663d02e..4bb6661e 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -193,7 +193,7 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) masterNode :=* rocket.masterNode val slaveNode = new TLInputNode() { override def reverse = true } - rocket.slaveNode :*= slaveNode + rocket.slaveNode connectButDontMonitorSlaves slaveNode // Fully async interrupts need synchronizers. // Others need no synchronization. @@ -213,8 +213,8 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters val slaveNode = new TLAsyncInputNode() { override def reverse = true } val sink = LazyModule(new TLAsyncCrossingSink) - rocket.slaveNode :*= sink.node - sink.node :*= slaveNode + rocket.slaveNode connectButDontMonitorSlaves sink.node + sink.node connectButDontMonitorSlaves slaveNode // Fully async interrupts need synchronizers, // as do those coming from the periphery clock. @@ -237,8 +237,8 @@ class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Paramet val slaveNode = new TLRationalInputNode() { override def reverse = true } val sink = LazyModule(new TLRationalCrossingSink(SlowToFast)) - rocket.slaveNode :*= sink.node - sink.node :*= slaveNode + rocket.slaveNode connectButDontMonitorSlaves sink.node + sink.node connectButDontMonitorSlaves slaveNode // Fully async interrupts need synchronizers. // Those coming from periphery clock need a From 289ef30dbc1d82b4d045a7693e9d1d12a3a269be Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 27 Jul 2017 15:44:51 -0700 Subject: [PATCH 4/5] coreplex: change AsynchronousCrossing.sync default to 3 --- src/main/scala/coreplex/BaseCoreplex.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala index 7c7be713..157adfb5 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/coreplex/BaseCoreplex.scala @@ -13,7 +13,7 @@ import freechips.rocketchip.util._ sealed trait CoreplexClockCrossing case class SynchronousCrossing(params: BufferParams = BufferParams.default) extends CoreplexClockCrossing case class RationalCrossing(direction: RationalDirection = FastToSlow) extends CoreplexClockCrossing -case class AsynchronousCrossing(depth: Int, sync: Int = 2) extends CoreplexClockCrossing +case class AsynchronousCrossing(depth: Int, sync: Int = 3) extends CoreplexClockCrossing /** BareCoreplex is the root class for creating a coreplex sub-system */ abstract class BareCoreplex(implicit p: Parameters) extends LazyModule with BindingScope { From b64b87ad0778582bb8583567d1d653f61f230a28 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 27 Jul 2017 17:30:51 -0700 Subject: [PATCH 5/5] tile: add option for tile boundary buffers --- src/main/scala/tile/RocketTile.scala | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index 4bb6661e..7afcb64d 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -17,7 +17,8 @@ case class RocketTileParams( dcache: Option[DCacheParams] = Some(DCacheParams()), rocc: Seq[RoCCParams] = Nil, btb: Option[BTBParams] = Some(BTBParams()), - dataScratchpadBytes: Int = 0) extends TileParams { + dataScratchpadBytes: Int = 0, + boundaryBufferParams: BufferParams = BufferParams.flow) extends TileParams { require(icache.isDefined) require(dcache.isDefined) } @@ -171,7 +172,11 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p: val periphIntNode = IntInputNode() val coreIntNode = IntInputNode() val intXbar = LazyModule(new IntXbar) + val masterBuffer = LazyModule(new TLBuffer(rtp.boundaryBufferParams)) + val slaveBuffer = LazyModule(new TLBuffer(rtp.boundaryBufferParams)) + masterBuffer.node :=* rocket.masterNode + rocket.slaveNode connectButDontMonitorSlaves slaveBuffer.node rocket.intNode := intXbar.intnode lazy val module = new LazyModuleImp(this) { @@ -190,10 +195,10 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p: class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) { val masterNode = TLOutputNode() - masterNode :=* rocket.masterNode + masterNode :=* masterBuffer.node val slaveNode = new TLInputNode() { override def reverse = true } - rocket.slaveNode connectButDontMonitorSlaves slaveNode + slaveBuffer.node connectButDontMonitorSlaves slaveNode // Fully async interrupts need synchronizers. // Others need no synchronization. @@ -208,12 +213,12 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) { val masterNode = TLAsyncOutputNode() val source = LazyModule(new TLAsyncCrossingSource) - source.node :=* rocket.masterNode + source.node :=* masterBuffer.node masterNode :=* source.node val slaveNode = new TLAsyncInputNode() { override def reverse = true } val sink = LazyModule(new TLAsyncCrossingSink) - rocket.slaveNode connectButDontMonitorSlaves sink.node + slaveBuffer.node connectButDontMonitorSlaves sink.node sink.node connectButDontMonitorSlaves slaveNode // Fully async interrupts need synchronizers, @@ -232,12 +237,12 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) { val masterNode = TLRationalOutputNode() val source = LazyModule(new TLRationalCrossingSource) - source.node :=* rocket.masterNode + source.node :=* masterBuffer.node masterNode :=* source.node val slaveNode = new TLRationalInputNode() { override def reverse = true } val sink = LazyModule(new TLRationalCrossingSink(SlowToFast)) - rocket.slaveNode connectButDontMonitorSlaves sink.node + slaveBuffer.node connectButDontMonitorSlaves sink.node sink.node connectButDontMonitorSlaves slaveNode // Fully async interrupts need synchronizers.