Merge pull request #830 from freechipsproject/flip-dts-idtim

Flip dts itim and dtim references

src/main/scala/rocket/Frontend.scala

@@ -53,9 +53,9 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
   val perf = new FrontendPerfEvents().asInput
 }
 
-class Frontend(val icacheParams: ICacheParams, hartid: Int, owner: => Option[Device] = None)(implicit p: Parameters) extends LazyModule {
+class Frontend(val icacheParams: ICacheParams, hartid: Int)(implicit p: Parameters) extends LazyModule {
   lazy val module = new FrontendModule(this)
-  val icache = LazyModule(new ICache(icacheParams, hartid, owner))
+  val icache = LazyModule(new ICache(icacheParams, hartid))
   val masterNode = TLOutputNode()
   val slaveNode = TLInputNode()
 
@@ -185,8 +185,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
 /** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
 trait HasICacheFrontend extends CanHavePTW with HasTileLinkMasterPort {
   val module: HasICacheFrontendModule
-  def itimOwner : Option[Device] = None
-  val frontend = LazyModule(new Frontend(tileParams.icache.get, hartid: Int, itimOwner))
+  val frontend = LazyModule(new Frontend(tileParams.icache.get, hartid: Int))
   val hartid: Int
   tileBus.node := frontend.masterNode
   nPTWPorts += 1

src/main/scala/rocket/ICache.scala

@@ -35,19 +35,12 @@ class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICache
   val addr = UInt(width = vaddrBits)
 }
 
-class ICache(val icacheParams: ICacheParams, val hartid: Int, owner: => Option[Device] = None)(implicit p: Parameters) extends LazyModule {
+class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parameters) extends LazyModule {
   lazy val module = new ICacheModule(this)
   val masterNode = TLClientNode(TLClientParameters(name = s"Core ${hartid} ICache"))
 
-  val device = new SimpleDevice("itim", Seq("sifive,itim0")) {
-      override def describe(resources: ResourceBindings): Description = {
-      val extra = owner.map(x => ("sifive,cpu" -> Seq(ResourceReference(x.label))))
-      val Description(name, mapping) = super.describe(resources)
-      Description(name, mapping ++ extra)
-    }
-  }
-
   val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
+  val device = new SimpleDevice("itim", Seq("sifive,itim0"))
   val slaveNode = icacheParams.itimAddr.map { itimAddr =>
     val wordBytes = icacheParams.fetchBytes
     TLManagerNode(Seq(TLManagerPortParameters(

src/main/scala/rocket/RocketTiles.scala

@@ -31,6 +31,7 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
 
   private def ofInt(x: Int) = Seq(ResourceInt(BigInt(x)))
   private def ofStr(x: String) = Seq(ResourceString(x))
+  private def ofRef(x: Device) = Seq(ResourceReference(x.label))
 
   val cpuDevice = new Device {
     def describe(resources: ResourceBindings): Description = {
@@ -47,6 +48,12 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
         "d-cache-sets"         -> ofInt(d.nSets),
         "d-cache-size"         -> ofInt(d.nSets * d.nWays * block))).getOrElse(Map())
 
+      val dtim = scratch.map(d => Map(
+        "sifive,dtim"          -> ofRef(d.device))).getOrElse(Map())
+
+      val itim = if (!frontend.icache.slaveNode.isDefined) Map() else Map(
+        "sifive,itim"          -> ofRef(frontend.icache.device))
+
       val icache = rocketParams.icache.map(i => Map(
         "i-cache-block-size"   -> ofInt(block),
         "i-cache-sets"         -> ofInt(i.nSets),
@@ -86,13 +93,9 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
         "status"               -> ofStr("okay"),
         "clock-frequency"      -> Seq(ResourceInt(rocketParams.core.bootFreqHz)),
         "riscv,isa"            -> ofStr(isa))
-        ++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb)
+        ++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb ++ dtim ++itim)
     }
   }
-
-  override def dtimOwner = Some(cpuDevice)
-  override def itimOwner = Some(cpuDevice)
-
   val intcDevice = new Device {
     def describe(resources: ResourceBindings): Description = {
       Description(s"cpus/cpu@${hartid}/interrupt-controller", Map(

src/main/scala/rocket/ScratchpadSlavePort.scala

@@ -13,16 +13,9 @@ import uncore.tilelink2._
 import uncore.util._
 import util._
 
-class ScratchpadSlavePort(address: AddressSet, owner: => Option[Device] = None)(implicit p: Parameters) extends LazyModule
+class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends LazyModule
     with HasCoreParameters {
-  val device = new SimpleDevice("dtim", Seq("sifive,dtim0")) {
-    override def describe(resources: ResourceBindings): Description = {
-      val extra = owner.map(x => ("sifive,cpu" -> Seq(ResourceReference(x.label))))
-      val Description(name, mapping) = super.describe(resources)
-      Description(name, mapping ++ extra)
-    }
-  }
-
+  val device = new SimpleDevice("dtim", Seq("sifive,dtim0"))
   val node = TLManagerNode(Seq(TLManagerPortParameters(
     Seq(TLManagerParameters(
       address            = List(address),
@@ -109,7 +102,6 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend with HasCor
   val module: CanHaveScratchpadModule
 
   val slaveNode = TLInputNode() // Up to two uses for this input node:
-  def dtimOwner: Option[Device] = None // who owns the Scratchpad?
 
   // 1) Frontend always exists, but may or may not have a scratchpad node
   val fg = LazyModule(new TLFragmenter(fetchWidth*coreInstBytes, p(CacheBlockBytes), earlyAck=true))
@@ -120,7 +112,7 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend with HasCor
 
   // 2) ScratchpadSlavePort always has a node, but only exists when the HellaCache has a scratchpad
   val scratch = tileParams.dcache.flatMap(d => d.scratch.map(s =>
-    LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), dtimOwner))))
+    LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1)))))
   scratch foreach { lm => lm.node := TLFragmenter(xLen/8, p(CacheBlockBytes), earlyAck=true)(slaveNode) }
 
   def findScratchpadFromICache: Option[AddressSet] = scratch.map { s =>