202 lines
7.1 KiB
Scala
202 lines
7.1 KiB
Scala
// See LICENSE.Berkeley for license details.
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// See LICENSE.SiFive for license details.
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package rocket
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import Chisel._
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import Chisel.ImplicitConversions._
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import chisel3.core.withReset
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import config._
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import coreplex._
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import diplomacy._
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import uncore.tilelink2._
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import tile._
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import util._
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class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
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val pc = UInt(width = vaddrBitsExtended)
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val speculative = Bool()
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}
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class FrontendExceptions extends Bundle {
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val pf = new Bundle {
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val inst = Bool()
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}
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val ae = new Bundle {
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val inst = Bool()
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}
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}
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class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) {
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val btb = Valid(new BTBResp)
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val pc = UInt(width = vaddrBitsExtended) // ID stage PC
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val data = UInt(width = fetchWidth * coreInstBits)
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val mask = Bits(width = fetchWidth)
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val xcpt = new FrontendExceptions
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val replay = Bool()
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}
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class FrontendPerfEvents extends Bundle {
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val acquire = Bool()
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val tlbMiss = Bool()
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}
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class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
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val req = Valid(new FrontendReq)
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val sfence = Valid(new SFenceReq)
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val resp = Decoupled(new FrontendResp).flip
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val btb_update = Valid(new BTBUpdate)
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val bht_update = Valid(new BHTUpdate)
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val ras_update = Valid(new RASUpdate)
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val flush_icache = Bool(OUTPUT)
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val npc = UInt(INPUT, width = vaddrBitsExtended)
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val perf = new FrontendPerfEvents().asInput
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}
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class Frontend(val icacheParams: ICacheParams, hartid: Int)(implicit p: Parameters) extends LazyModule {
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lazy val module = new FrontendModule(this)
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val icache = LazyModule(new ICache(icacheParams, hartid))
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val masterNode = TLOutputNode()
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val slaveNode = TLInputNode()
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masterNode := icache.masterNode
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// Avoid breaking tile dedup due to address constants in the monitor
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icache.slaveNode.map { _ connectButDontMonitor slaveNode }
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}
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class FrontendBundle(outer: Frontend) extends CoreBundle()(outer.p) {
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val cpu = new FrontendIO().flip
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val ptw = new TLBPTWIO()
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val tl_out = outer.masterNode.bundleOut
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val tl_in = outer.slaveNode.bundleIn
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val resetVector = UInt(INPUT, vaddrBitsExtended)
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val hartid = UInt(INPUT, hartIdLen)
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}
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class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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with HasCoreParameters
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with HasL1ICacheParameters {
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val io = new FrontendBundle(outer)
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implicit val edge = outer.masterNode.edgesOut.head
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val icache = outer.icache.module
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require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes)
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val tlb = Module(new TLB(log2Ceil(coreInstBytes*fetchWidth), nTLBEntries))
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val fq = withReset(reset || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 4, flow = true)) }
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val s0_valid = io.cpu.req.valid || !fq.io.mask(fq.io.mask.getWidth-2)
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val s1_pc = Reg(UInt(width=vaddrBitsExtended))
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val s1_speculative = Reg(Bool())
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val s2_valid = RegInit(false.B)
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val s2_pc = Reg(init=io.resetVector)
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val s2_btb_resp_valid = Reg(init=Bool(false))
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val s2_btb_resp_bits = Reg(new BTBResp)
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val s2_tlb_resp = Reg(tlb.io.resp)
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val s2_xcpt = !s2_tlb_resp.miss && fq.io.enq.bits.xcpt.asUInt.orR
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val s2_speculative = Reg(init=Bool(false))
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val fetchBytes = coreInstBytes * fetchWidth
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val s1_base_pc = ~(~s1_pc | (fetchBytes - 1))
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val ntpc = s1_base_pc + fetchBytes.U
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val predicted_npc = Wire(init = ntpc)
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val predicted_taken = Wire(init = Bool(false))
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val s2_replay = Wire(Bool())
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s2_replay := (s2_valid && !fq.io.enq.fire()) || RegNext(s2_replay && !s0_valid, true.B)
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val npc = Mux(s2_replay, s2_pc, predicted_npc)
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s1_pc := io.cpu.npc
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// consider RVC fetches across blocks to be non-speculative if the first
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// part was non-speculative
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val s0_speculative =
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if (usingCompressed) s1_speculative || s2_valid && !s2_speculative || predicted_taken
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else Bool(true)
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s1_speculative := Mux(io.cpu.req.valid, io.cpu.req.bits.speculative, Mux(s2_replay, s2_speculative, s0_speculative))
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s2_valid := false
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when (!s2_replay && !io.cpu.req.valid) {
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s2_valid := true
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s2_pc := s1_pc
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s2_speculative := s1_speculative
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s2_tlb_resp := tlb.io.resp
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}
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if (usingBTB) {
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val btb = Module(new BTB)
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btb.io.req.valid := false
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btb.io.req.bits.addr := s1_pc
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btb.io.btb_update := io.cpu.btb_update
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btb.io.bht_update := io.cpu.bht_update
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btb.io.ras_update := io.cpu.ras_update
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when (!s2_replay) {
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btb.io.req.valid := true
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s2_btb_resp_valid := btb.io.resp.valid
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s2_btb_resp_bits := btb.io.resp.bits
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}
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when (btb.io.resp.valid && btb.io.resp.bits.taken) {
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predicted_npc := btb.io.resp.bits.target.sextTo(vaddrBitsExtended)
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predicted_taken := Bool(true)
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}
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// push RAS speculatively
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btb.io.ras_update.valid := btb.io.req.valid && btb.io.resp.valid && btb.io.resp.bits.cfiType.isOneOf(CFIType.call, CFIType.ret)
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val returnAddrLSBs = btb.io.resp.bits.bridx +& 1
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btb.io.ras_update.bits.returnAddr :=
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Mux(returnAddrLSBs(log2Ceil(fetchWidth)), ntpc, s1_base_pc | ((returnAddrLSBs << log2Ceil(coreInstBytes)) & (fetchBytes - 1)))
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btb.io.ras_update.bits.cfiType := btb.io.resp.bits.cfiType
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btb.io.ras_update.bits.prediction.valid := true
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}
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io.ptw <> tlb.io.ptw
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tlb.io.req.valid := !s2_replay
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tlb.io.req.bits.vaddr := s1_pc
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tlb.io.req.bits.passthrough := Bool(false)
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tlb.io.req.bits.instruction := Bool(true)
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tlb.io.req.bits.sfence := io.cpu.sfence
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tlb.io.req.bits.size := log2Ceil(coreInstBytes*fetchWidth)
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icache.io.hartid := io.hartid
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icache.io.req.valid := s0_valid
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icache.io.req.bits.addr := io.cpu.npc
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icache.io.invalidate := io.cpu.flush_icache
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icache.io.s1_paddr := tlb.io.resp.paddr
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icache.io.s2_vaddr := s2_pc
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icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || s2_replay
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icache.io.s2_kill := s2_valid && (s2_speculative && !s2_tlb_resp.cacheable || s2_xcpt)
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fq.io.enq.valid := s2_valid && (icache.io.resp.valid || icache.io.s2_kill)
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fq.io.enq.bits.pc := s2_pc
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io.cpu.npc := ~(~Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) | (coreInstBytes-1)) // discard LSB(s)
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fq.io.enq.bits.data := icache.io.resp.bits
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fq.io.enq.bits.mask := UInt((1 << fetchWidth)-1) << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
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fq.io.enq.bits.xcpt := s2_tlb_resp
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fq.io.enq.bits.replay := icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt
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fq.io.enq.bits.btb.valid := s2_btb_resp_valid
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fq.io.enq.bits.btb.bits := s2_btb_resp_bits
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io.cpu.resp <> fq.io.deq
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// performance events
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io.cpu.perf.acquire := edge.done(icache.io.tl_out(0).a)
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io.cpu.perf.tlbMiss := io.ptw.req.fire()
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}
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/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
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trait HasICacheFrontend extends CanHavePTW with HasTileLinkMasterPort {
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val module: HasICacheFrontendModule
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val frontend = LazyModule(new Frontend(tileParams.icache.get, hartid: Int))
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val hartid: Int
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tileBus.node := frontend.masterNode
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nPTWPorts += 1
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}
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trait HasICacheFrontendBundle extends HasTileLinkMasterPortBundle {
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val outer: HasICacheFrontend
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}
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trait HasICacheFrontendModule extends CanHavePTWModule with HasTileLinkMasterPortModule {
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val outer: HasICacheFrontend
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ptwPorts += outer.frontend.module.io.ptw
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}
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