From fbcd6f0eb2b874de818c8f4489dc4d0d48661743 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 28 Jun 2017 21:28:08 -0700 Subject: [PATCH 1/3] Revert "rocket: link itim to its cpu" This reverts commit 48390ed604e12dbcb1b119cb2d4eb1c645ea8f7e. --- src/main/scala/rocket/Frontend.scala | 7 +++---- src/main/scala/rocket/ICache.scala | 11 ++--------- src/main/scala/rocket/RocketTiles.scala | 1 - 3 files changed, 5 insertions(+), 14 deletions(-) diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala index baf45dc7..44f51d32 100644 --- a/src/main/scala/rocket/Frontend.scala +++ b/src/main/scala/rocket/Frontend.scala @@ -53,9 +53,9 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) { val perf = new FrontendPerfEvents().asInput } -class Frontend(val icacheParams: ICacheParams, hartid: Int, owner: => Option[Device] = None)(implicit p: Parameters) extends LazyModule { +class Frontend(val icacheParams: ICacheParams, hartid: Int)(implicit p: Parameters) extends LazyModule { lazy val module = new FrontendModule(this) - val icache = LazyModule(new ICache(icacheParams, hartid, owner)) + val icache = LazyModule(new ICache(icacheParams, hartid)) val masterNode = TLOutputNode() val slaveNode = TLInputNode() @@ -185,8 +185,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) /** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */ trait HasICacheFrontend extends CanHavePTW with HasTileLinkMasterPort { val module: HasICacheFrontendModule - def itimOwner : Option[Device] = None - val frontend = LazyModule(new Frontend(tileParams.icache.get, hartid: Int, itimOwner)) + val frontend = LazyModule(new Frontend(tileParams.icache.get, hartid: Int)) val hartid: Int tileBus.node := frontend.masterNode nPTWPorts += 1 diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index ec093623..dfb240f4 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -35,19 +35,12 @@ class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICache val addr = UInt(width = vaddrBits) } -class ICache(val icacheParams: ICacheParams, val hartid: Int, owner: => Option[Device] = None)(implicit p: Parameters) extends LazyModule { +class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parameters) extends LazyModule { lazy val module = new ICacheModule(this) val masterNode = TLClientNode(TLClientParameters(name = s"Core ${hartid} ICache")) - val device = new SimpleDevice("itim", Seq("sifive,itim0")) { - override def describe(resources: ResourceBindings): Description = { - val extra = owner.map(x => ("sifive,cpu" -> Seq(ResourceReference(x.label)))) - val Description(name, mapping) = super.describe(resources) - Description(name, mapping ++ extra) - } - } - val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes + val device = new SimpleDevice("itim", Seq("sifive,itim0")) val slaveNode = icacheParams.itimAddr.map { itimAddr => val wordBytes = icacheParams.fetchBytes TLManagerNode(Seq(TLManagerPortParameters( diff --git a/src/main/scala/rocket/RocketTiles.scala b/src/main/scala/rocket/RocketTiles.scala index ab118915..4e5fccad 100644 --- a/src/main/scala/rocket/RocketTiles.scala +++ b/src/main/scala/rocket/RocketTiles.scala @@ -91,7 +91,6 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p } override def dtimOwner = Some(cpuDevice) - override def itimOwner = Some(cpuDevice) val intcDevice = new Device { def describe(resources: ResourceBindings): Description = { From 7d6f8d48f2d18c226f81c810d6e466b6de96f2ae Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 28 Jun 2017 21:28:16 -0700 Subject: [PATCH 2/3] Revert "rocket: link dtim to its cpu" This reverts commit e6c2d446ccf85a409969e8b298fa5c6baca4ff4a. --- src/main/scala/rocket/RocketTiles.scala | 3 --- src/main/scala/rocket/ScratchpadSlavePort.scala | 14 +++----------- 2 files changed, 3 insertions(+), 14 deletions(-) diff --git a/src/main/scala/rocket/RocketTiles.scala b/src/main/scala/rocket/RocketTiles.scala index 4e5fccad..a393cb15 100644 --- a/src/main/scala/rocket/RocketTiles.scala +++ b/src/main/scala/rocket/RocketTiles.scala @@ -89,9 +89,6 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p ++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb) } } - - override def dtimOwner = Some(cpuDevice) - val intcDevice = new Device { def describe(resources: ResourceBindings): Description = { Description(s"cpus/cpu@${hartid}/interrupt-controller", Map( diff --git a/src/main/scala/rocket/ScratchpadSlavePort.scala b/src/main/scala/rocket/ScratchpadSlavePort.scala index 12035ee8..667cc157 100644 --- a/src/main/scala/rocket/ScratchpadSlavePort.scala +++ b/src/main/scala/rocket/ScratchpadSlavePort.scala @@ -13,16 +13,9 @@ import uncore.tilelink2._ import uncore.util._ import util._ -class ScratchpadSlavePort(address: AddressSet, owner: => Option[Device] = None)(implicit p: Parameters) extends LazyModule +class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends LazyModule with HasCoreParameters { - val device = new SimpleDevice("dtim", Seq("sifive,dtim0")) { - override def describe(resources: ResourceBindings): Description = { - val extra = owner.map(x => ("sifive,cpu" -> Seq(ResourceReference(x.label)))) - val Description(name, mapping) = super.describe(resources) - Description(name, mapping ++ extra) - } - } - + val device = new SimpleDevice("dtim", Seq("sifive,dtim0")) val node = TLManagerNode(Seq(TLManagerPortParameters( Seq(TLManagerParameters( address = List(address), @@ -109,7 +102,6 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend with HasCor val module: CanHaveScratchpadModule val slaveNode = TLInputNode() // Up to two uses for this input node: - def dtimOwner: Option[Device] = None // who owns the Scratchpad? // 1) Frontend always exists, but may or may not have a scratchpad node val fg = LazyModule(new TLFragmenter(fetchWidth*coreInstBytes, p(CacheBlockBytes), earlyAck=true)) @@ -120,7 +112,7 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend with HasCor // 2) ScratchpadSlavePort always has a node, but only exists when the HellaCache has a scratchpad val scratch = tileParams.dcache.flatMap(d => d.scratch.map(s => - LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), dtimOwner)))) + LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1))))) scratch foreach { lm => lm.node := TLFragmenter(xLen/8, p(CacheBlockBytes), earlyAck=true)(slaveNode) } def findScratchpadFromICache: Option[AddressSet] = scratch.map { s => From 5edc4546e3c00c198f8f8e057f4492e367967baf Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 28 Jun 2017 21:40:01 -0700 Subject: [PATCH 3/3] rocket: add dtim and itim refs to cpus --- src/main/scala/rocket/RocketTiles.scala | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/main/scala/rocket/RocketTiles.scala b/src/main/scala/rocket/RocketTiles.scala index a393cb15..4811199b 100644 --- a/src/main/scala/rocket/RocketTiles.scala +++ b/src/main/scala/rocket/RocketTiles.scala @@ -31,6 +31,7 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p private def ofInt(x: Int) = Seq(ResourceInt(BigInt(x))) private def ofStr(x: String) = Seq(ResourceString(x)) + private def ofRef(x: Device) = Seq(ResourceReference(x.label)) val cpuDevice = new Device { def describe(resources: ResourceBindings): Description = { @@ -47,6 +48,12 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p "d-cache-sets" -> ofInt(d.nSets), "d-cache-size" -> ofInt(d.nSets * d.nWays * block))).getOrElse(Map()) + val dtim = scratch.map(d => Map( + "sifive,dtim" -> ofRef(d.device))).getOrElse(Map()) + + val itim = if (!frontend.icache.slaveNode.isDefined) Map() else Map( + "sifive,itim" -> ofRef(frontend.icache.device)) + val icache = rocketParams.icache.map(i => Map( "i-cache-block-size" -> ofInt(block), "i-cache-sets" -> ofInt(i.nSets), @@ -86,7 +93,7 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p "status" -> ofStr("okay"), "clock-frequency" -> Seq(ResourceInt(rocketParams.core.bootFreqHz)), "riscv,isa" -> ofStr(isa)) - ++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb) + ++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb ++ dtim ++itim) } } val intcDevice = new Device {