From 7d7d7f49f98ff94328df7efa2109b7d13c2f8e52 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Tue, 20 Mar 2012 15:21:36 -0700 Subject: [PATCH] change the tlb arbiter to a round robing one --- rocket/src/main/scala/cpu.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala index e8a0d6da..aa03f75a 100644 --- a/rocket/src/main/scala/cpu.scala +++ b/rocket/src/main/scala/cpu.scala @@ -37,7 +37,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal) { vu = new vu() // cpu, vector prefetch, and vector use the DTLB - val dtlbarb = new Arbiter(3)({new ioDTLB_CPU_req_bundle()}) + val dtlbarb = new RRArbiter(3)({new ioDTLB_CPU_req_bundle()}) val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2up(3))) when( dtlb.io.cpu_req.ready && dtlbarb.io.out.valid ) { dtlbchosen := dtlbarb.io.chosen }