riscv/rocket-chip
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[commitlog] Added privilege-level to output

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This commit is contained in:
Christopher Celio 2015-09-11 16:08:12 -07:00
parent 53a02a62c8
commit 7d14abf262
2 changed files with 6 additions and 6 deletions
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2
rocket/src/main/scala/fpu.scala
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@ -386,7 +386,7 @@ class FPU extends CoreModule
when (load_wb) { when (load_wb) {
regfile(load_wb_tag) := load_wb_data_recoded regfile(load_wb_tag) := load_wb_data_recoded
if (EnableCommitLog) { if (EnableCommitLog) {
printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32), load_wb_data) // TODO see what happens, either change spike to sext, or us or whatever. printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32), load_wb_data)
} }
} }

10
rocket/src/main/scala/rocket.scala
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@ -502,20 +502,20 @@ class Rocket extends CoreModule
val wfd = wb_ctrl.wfd val wfd = wb_ctrl.wfd
val wxd = wb_ctrl.wxd val wxd = wb_ctrl.wxd
val has_data = wb_wen && !wb_set_sboard val has_data = wb_wen && !wb_set_sboard
val priv = csr.io.status.prv
when (wb_valid) { when (wb_valid) {
// TODO add privileged level
when (wfd) { when (wfd) {
printf ("0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", pc, inst, rd, rd+UInt(32)) printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", priv, pc, inst, rd, rd+UInt(32))
} }
.elsewhen (wxd && rd != UInt(0) && has_data) { .elsewhen (wxd && rd != UInt(0) && has_data) {
printf ("0x%x (0x%x) x%d 0x%x\n", pc, inst, rd, rf_wdata) printf ("%d 0x%x (0x%x) x%d 0x%x\n", priv, pc, inst, rd, rf_wdata)
} }
.elsewhen (wxd && rd != UInt(0) && !has_data) { .elsewhen (wxd && rd != UInt(0) && !has_data) {
printf ("0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", pc, inst, rd, rd) printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", priv, pc, inst, rd, rd)
} }
.otherwise { // !wxd || (wxd && rd == 0) .otherwise { // !wxd || (wxd && rd == 0)
printf ("0x%x (0x%x)\n", pc, inst) printf ("%d 0x%x (0x%x)\n", priv, pc, inst)
} }
} }