From 7d14abf26215563b32898acb6729b21fab083f42 Mon Sep 17 00:00:00 2001 From: Christopher Celio Date: Fri, 11 Sep 2015 16:08:12 -0700 Subject: [PATCH] [commitlog] Added privilege-level to output --- rocket/src/main/scala/fpu.scala | 2 +- rocket/src/main/scala/rocket.scala | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala index 56755e42..ede8679c 100644 --- a/rocket/src/main/scala/fpu.scala +++ b/rocket/src/main/scala/fpu.scala @@ -386,7 +386,7 @@ class FPU extends CoreModule when (load_wb) { regfile(load_wb_tag) := load_wb_data_recoded if (EnableCommitLog) { - printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32), load_wb_data) // TODO see what happens, either change spike to sext, or us or whatever. + printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32), load_wb_data) } } diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala index 157b55ed..a04a64e6 100644 --- a/rocket/src/main/scala/rocket.scala +++ b/rocket/src/main/scala/rocket.scala @@ -502,20 +502,20 @@ class Rocket extends CoreModule val wfd = wb_ctrl.wfd val wxd = wb_ctrl.wxd val has_data = wb_wen && !wb_set_sboard + val priv = csr.io.status.prv when (wb_valid) { - // TODO add privileged level when (wfd) { - printf ("0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", pc, inst, rd, rd+UInt(32)) + printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", priv, pc, inst, rd, rd+UInt(32)) } .elsewhen (wxd && rd != UInt(0) && has_data) { - printf ("0x%x (0x%x) x%d 0x%x\n", pc, inst, rd, rf_wdata) + printf ("%d 0x%x (0x%x) x%d 0x%x\n", priv, pc, inst, rd, rf_wdata) } .elsewhen (wxd && rd != UInt(0) && !has_data) { - printf ("0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", pc, inst, rd, rd) + printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", priv, pc, inst, rd, rd) } .otherwise { // !wxd || (wxd && rd == 0) - printf ("0x%x (0x%x)\n", pc, inst) + printf ("%d 0x%x (0x%x)\n", priv, pc, inst) } }