riscv/rocket-chip
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Don't pollute BTB with PC+4 target predictions

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This commit is contained in:
Andrew Waterman 2014-10-14 17:28:37 -07:00
parent cde7c9d869
commit 7bb7299018
2 changed files with 7 additions and 7 deletions
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8
rocket/src/main/scala/btb.scala
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@ -75,7 +75,7 @@ class BTBUpdate extends Bundle with BTBParameters {
val isJump = Bool() val isJump = Bool()
val isCall = Bool() val isCall = Bool()
val isReturn = Bool() val isReturn = Bool()
val incorrectTarget = Bool() val mispredict = Bool()
} }
class BTBResp extends Bundle with BTBParameters { class BTBResp extends Bundle with BTBParameters {
@ -138,8 +138,8 @@ class BTB extends Module with BTBParameters {
} }
val updateHit = r_update.bits.prediction.valid val updateHit = r_update.bits.prediction.valid
val updateValid = r_update.bits.incorrectTarget || updateHit && Bool(nBHT > 0) val updateValid = r_update.bits.mispredict || updateHit && Bool(nBHT > 0)
val updateTarget = updateValid && r_update.bits.incorrectTarget val updateTarget = updateValid && r_update.bits.mispredict && r_update.bits.taken
val useUpdatePageHit = updatePageHit.orR val useUpdatePageHit = updatePageHit.orR
val doIdxPageRepl = updateTarget && !useUpdatePageHit val doIdxPageRepl = updateTarget && !useUpdatePageHit
@ -208,7 +208,7 @@ class BTB extends Module with BTBParameters {
val update_btb_hit = io.update.bits.prediction.valid val update_btb_hit = io.update.bits.prediction.valid
when (io.update.valid && update_btb_hit && !io.update.bits.isJump) { when (io.update.valid && update_btb_hit && !io.update.bits.isJump) {
bht.update(io.update.bits.pc, io.update.bits.prediction.bits.bht, bht.update(io.update.bits.pc, io.update.bits.prediction.bits.bht,
io.update.bits.taken, io.update.bits.incorrectTarget) io.update.bits.taken, io.update.bits.mispredict)
} }
when (!res.value(0) && !Mux1H(hits, isJump)) { io.resp.bits.taken := false } when (!res.value(0) && !Mux1H(hits, isJump)) { io.resp.bits.taken := false }
io.resp.bits.bht := res io.resp.bits.bht := res

6
rocket/src/main/scala/ctrl.scala
View File

@ -652,11 +652,11 @@ class Control extends Module
Mux(replay_wb, PC_WB, // replay Mux(replay_wb, PC_WB, // replay
PC_MEM))) PC_MEM)))
io.imem.btb_update.valid := mem_reg_branch || mem_reg_jal || mem_reg_jalr io.imem.btb_update.valid := (mem_reg_branch || io.imem.btb_update.bits.isJump) && !take_pc_wb
io.imem.btb_update.bits.prediction.valid := mem_reg_btb_hit io.imem.btb_update.bits.prediction.valid := mem_reg_btb_hit
io.imem.btb_update.bits.prediction.bits := mem_reg_btb_resp io.imem.btb_update.bits.prediction.bits := mem_reg_btb_resp
io.imem.btb_update.bits.taken := mem_reg_jal || mem_reg_branch && io.dpath.mem_br_taken io.imem.btb_update.bits.taken := mem_reg_branch && io.dpath.mem_br_taken || io.imem.btb_update.bits.isJump
io.imem.btb_update.bits.incorrectTarget := take_pc_mem io.imem.btb_update.bits.mispredict := take_pc_mem
io.imem.btb_update.bits.isJump := mem_reg_jal || mem_reg_jalr io.imem.btb_update.bits.isJump := mem_reg_jal || mem_reg_jalr
io.imem.btb_update.bits.isCall := mem_reg_wen && io.dpath.mem_waddr(0) io.imem.btb_update.bits.isCall := mem_reg_wen && io.dpath.mem_waddr(0)
io.imem.btb_update.bits.isReturn := mem_reg_jalr && io.dpath.mem_rs1_ra io.imem.btb_update.bits.isReturn := mem_reg_jalr && io.dpath.mem_rs1_ra