diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala
index 0f1ee962..dae63215 100644
--- a/rocket/src/main/scala/btb.scala
+++ b/rocket/src/main/scala/btb.scala
@@ -75,7 +75,7 @@ class BTBUpdate extends Bundle with BTBParameters {
   val isJump = Bool()
   val isCall = Bool()
   val isReturn = Bool()
-  val incorrectTarget = Bool()
+  val mispredict = Bool()
 }
 
 class BTBResp extends Bundle with BTBParameters {
@@ -138,8 +138,8 @@ class BTB extends Module with BTBParameters {
   }
 
   val updateHit = r_update.bits.prediction.valid
-  val updateValid = r_update.bits.incorrectTarget || updateHit && Bool(nBHT > 0)
-  val updateTarget = updateValid && r_update.bits.incorrectTarget
+  val updateValid = r_update.bits.mispredict || updateHit && Bool(nBHT > 0)
+  val updateTarget = updateValid && r_update.bits.mispredict && r_update.bits.taken
 
   val useUpdatePageHit = updatePageHit.orR
   val doIdxPageRepl = updateTarget && !useUpdatePageHit
@@ -208,7 +208,7 @@ class BTB extends Module with BTBParameters {
     val update_btb_hit = io.update.bits.prediction.valid
     when (io.update.valid && update_btb_hit && !io.update.bits.isJump) {
       bht.update(io.update.bits.pc, io.update.bits.prediction.bits.bht,
-                 io.update.bits.taken, io.update.bits.incorrectTarget)
+                 io.update.bits.taken, io.update.bits.mispredict)
     }
     when (!res.value(0) && !Mux1H(hits, isJump)) { io.resp.bits.taken := false }
     io.resp.bits.bht := res
diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index d72eba45..6ea50107 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -652,11 +652,11 @@ class Control extends Module
     Mux(replay_wb,        PC_WB,  // replay
                           PC_MEM)))
 
-  io.imem.btb_update.valid := mem_reg_branch || mem_reg_jal || mem_reg_jalr
+  io.imem.btb_update.valid := (mem_reg_branch || io.imem.btb_update.bits.isJump) && !take_pc_wb
   io.imem.btb_update.bits.prediction.valid := mem_reg_btb_hit
   io.imem.btb_update.bits.prediction.bits := mem_reg_btb_resp
-  io.imem.btb_update.bits.taken := mem_reg_jal || mem_reg_branch && io.dpath.mem_br_taken
-  io.imem.btb_update.bits.incorrectTarget := take_pc_mem
+  io.imem.btb_update.bits.taken := mem_reg_branch && io.dpath.mem_br_taken || io.imem.btb_update.bits.isJump
+  io.imem.btb_update.bits.mispredict := take_pc_mem
   io.imem.btb_update.bits.isJump := mem_reg_jal || mem_reg_jalr
   io.imem.btb_update.bits.isCall := mem_reg_wen && io.dpath.mem_waddr(0)
   io.imem.btb_update.bits.isReturn := mem_reg_jalr && io.dpath.mem_rs1_ra