riscv/rocket-chip
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Don't pollute BTB with PC+4 target predictions

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This commit is contained in:
Andrew Waterman
2014-10-14 17:28:37 -07:00
parent cde7c9d869
commit 7bb7299018
2 changed files with 7 additions and 7 deletions
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8
rocket/src/main/scala/btb.scala
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@ -75,7 +75,7 @@ class BTBUpdate extends Bundle with BTBParameters {
val isJump = Bool()
val isCall = Bool()
val isReturn = Bool()
val incorrectTarget = Bool()
val mispredict = Bool()
}
class BTBResp extends Bundle with BTBParameters {
@ -138,8 +138,8 @@ class BTB extends Module with BTBParameters {
}
val updateHit = r_update.bits.prediction.valid
val updateValid = r_update.bits.incorrectTarget || updateHit && Bool(nBHT > 0)
val updateTarget = updateValid && r_update.bits.incorrectTarget
val updateValid = r_update.bits.mispredict || updateHit && Bool(nBHT > 0)
val updateTarget = updateValid && r_update.bits.mispredict && r_update.bits.taken
val useUpdatePageHit = updatePageHit.orR
val doIdxPageRepl = updateTarget && !useUpdatePageHit
@ -208,7 +208,7 @@ class BTB extends Module with BTBParameters {
val update_btb_hit = io.update.bits.prediction.valid
when (io.update.valid && update_btb_hit && !io.update.bits.isJump) {
bht.update(io.update.bits.pc, io.update.bits.prediction.bits.bht,
io.update.bits.taken, io.update.bits.incorrectTarget)
io.update.bits.taken, io.update.bits.mispredict)
}
when (!res.value(0) && !Mux1H(hits, isJump)) { io.resp.bits.taken := false }
io.resp.bits.bht := res