riscv/rocket-chip
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coreplex: provide correct bus-width for ITIM blockers

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This commit is contained in:
Wesley W. Terpstra 2017-11-18 14:32:37 -08:00
parent 9e0c26f855
commit 7a1937242a
1 changed files with 1 additions and 1 deletions
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src/main/scala/coreplex/RocketCoreplex.scala
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@ -38,7 +38,7 @@ case class TileSlavePortParams(
(implicit p: Parameters, sourceInfo: SourceInfo): TLInwardNode = { (implicit p: Parameters, sourceInfo: SourceInfo): TLInwardNode = {
val tile_slave_blocker = val tile_slave_blocker =
blockerCtrlAddr blockerCtrlAddr
.map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes)) .map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes, coreplex.sbus.beatBytes))
.map(bp => LazyModule(new BasicBusBlocker(bp))) .map(bp => LazyModule(new BasicBusBlocker(bp)))
tile_slave_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves } tile_slave_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves }