From 7a1937242a44ebadcc176a8cc39e6579ce911bad Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sat, 18 Nov 2017 14:32:37 -0800 Subject: [PATCH] coreplex: provide correct bus-width for ITIM blockers --- src/main/scala/coreplex/RocketCoreplex.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala index 06e971a5..8d9f6e94 100644 --- a/src/main/scala/coreplex/RocketCoreplex.scala +++ b/src/main/scala/coreplex/RocketCoreplex.scala @@ -38,7 +38,7 @@ case class TileSlavePortParams( (implicit p: Parameters, sourceInfo: SourceInfo): TLInwardNode = { val tile_slave_blocker = blockerCtrlAddr - .map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes)) + .map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes, coreplex.sbus.beatBytes)) .map(bp => LazyModule(new BasicBusBlocker(bp))) tile_slave_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves }