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Chisel3 compatibility: use >>Int instead of >>UInt

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The latter doesn't contract widths anymore.
This commit is contained in:
Andrew Waterman 2015-08-04 13:15:17 -07:00
parent fb718f03c1
commit 798ddeb5f5
4 changed files with 10 additions and 10 deletions
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2
uncore/src/main/scala/cache.scala
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@ -87,7 +87,7 @@ class AMOALU extends CacheModule {
val word = io.typ === MT_W || io.typ === MT_WU || // Logic minimization: val word = io.typ === MT_W || io.typ === MT_WU || // Logic minimization:
io.typ === MT_B || io.typ === MT_BU io.typ === MT_B || io.typ === MT_BU
val mask = ~UInt(0,64) ^ (io.addr(2) << UInt(31)) val mask = ~UInt(0,64) ^ (io.addr(2) << 31)
val adder_out = (io.lhs & mask).toUInt + (rhs & mask) val adder_out = (io.lhs & mask).toUInt + (rhs & mask)
val cmp_lhs = Mux(word && !io.addr(2), io.lhs(31), io.lhs(63)) val cmp_lhs = Mux(word && !io.addr(2), io.lhs(31), io.lhs(63))

2
uncore/src/main/scala/ecc.scala
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@ -79,7 +79,7 @@ class SECCode extends Code
private def swizzle(z: UInt) = Vec((1 to n).filter(i => !isPow2(i)).map(i => z(i-1))).toBits private def swizzle(z: UInt) = Vec((1 to n).filter(i => !isPow2(i)).map(i => z(i-1))).toBits
def uncorrected = swizzle(y) def uncorrected = swizzle(y)
def corrected = swizzle(((y.toUInt << UInt(1)) ^ UIntToOH(s)) >> UInt(1)) def corrected = swizzle(((y.toUInt << 1) ^ UIntToOH(s)) >> 1)
def correctable = s.orR def correctable = s.orR
def uncorrectable = Bool(false) def uncorrectable = Bool(false)
} }

4
uncore/src/main/scala/htif.scala
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@ -96,7 +96,7 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
} }
} }
val rx_word_count = (rx_count >> UInt(log2Up(short_request_bits/w))) val rx_word_count = (rx_count >> log2Up(short_request_bits/w))
val rx_word_done = io.host.in.valid && rx_count(log2Up(short_request_bits/w)-1,0).andR val rx_word_done = io.host.in.valid && rx_count(log2Up(short_request_bits/w)-1,0).andR
val packet_ram_depth = long_request_bits/short_request_bits-1 val packet_ram_depth = long_request_bits/short_request_bits-1
val packet_ram = Mem(Bits(width = short_request_bits), packet_ram_depth) val packet_ram = Mem(Bits(width = short_request_bits), packet_ram_depth)
@ -173,7 +173,7 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
packet_ram(Cat(cnt, ui)) packet_ram(Cat(cnt, ui))
}.reverse.reduce(_##_) }.reverse.reduce(_##_)
val init_addr = addr.toUInt >> UInt(offsetBits-3) val init_addr = addr.toUInt >> (offsetBits-3)
io.mem.acquire.valid := state === state_mem_rreq || state === state_mem_wreq io.mem.acquire.valid := state === state_mem_rreq || state === state_mem_wreq
io.mem.acquire.bits := Mux(cmd === cmd_writemem, io.mem.acquire.bits := Mux(cmd === cmd_writemem,
PutBlock( PutBlock(

12
uncore/src/main/scala/tilelink.scala
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@ -1112,7 +1112,7 @@ trait AppendsArbiterId extends TileLinkArbiterLike {
def clientSourcedClientXactId(in: ClientSourcedWithId, id: Int) = def clientSourcedClientXactId(in: ClientSourcedWithId, id: Int) =
Cat(in.client_xact_id, UInt(id, log2Up(arbN))) Cat(in.client_xact_id, UInt(id, log2Up(arbN)))
def managerSourcedClientXactId(in: ManagerSourcedWithId) = def managerSourcedClientXactId(in: ManagerSourcedWithId) =
in.client_xact_id >> UInt(log2Up(arbN)) in.client_xact_id >> log2Up(arbN)
def arbIdx(in: ManagerSourcedWithId) = in.client_xact_id(log2Up(arbN)-1,0).toUInt def arbIdx(in: ManagerSourcedWithId) = in.client_xact_id(log2Up(arbN)-1,0).toUInt
} }
@ -1378,7 +1378,7 @@ class NASTIMasterIOTileLinkIOConverter extends TLModule with NASTIParameters {
dst = (if(dstIdBits > 0) io.nasti.r.bits.id(dst_off, tlClientXactIdBits + 1) else UInt(0)), dst = (if(dstIdBits > 0) io.nasti.r.bits.id(dst_off, tlClientXactIdBits + 1) else UInt(0)),
is_builtin_type = io.nasti.r.bits.id(0), is_builtin_type = io.nasti.r.bits.id(0),
g_type = Mux(io.nasti.r.bits.id(0), Grant.getDataBlockType, UInt(0)), // TODO: Assumes MI or MEI protocol g_type = Mux(io.nasti.r.bits.id(0), Grant.getDataBlockType, UInt(0)), // TODO: Assumes MI or MEI protocol
client_xact_id = io.nasti.r.bits.id >> UInt(1), client_xact_id = io.nasti.r.bits.id >> 1,
manager_xact_id = UInt(0), manager_xact_id = UInt(0),
addr_beat = tl_cnt_in, addr_beat = tl_cnt_in,
data = io.nasti.r.bits.data) data = io.nasti.r.bits.data)
@ -1389,7 +1389,7 @@ class NASTIMasterIOTileLinkIOConverter extends TLModule with NASTIParameters {
dst = (if(dstIdBits > 0) io.nasti.b.bits.id(dst_off, tlClientXactIdBits + 1) else UInt(0)), dst = (if(dstIdBits > 0) io.nasti.b.bits.id(dst_off, tlClientXactIdBits + 1) else UInt(0)),
is_builtin_type = Bool(true), is_builtin_type = Bool(true),
g_type = Mux(io.nasti.b.bits.id(0), Grant.voluntaryAckType, Grant.putAckType), g_type = Mux(io.nasti.b.bits.id(0), Grant.voluntaryAckType, Grant.putAckType),
client_xact_id = io.nasti.b.bits.id >> UInt(1), client_xact_id = io.nasti.b.bits.id >> 1,
manager_xact_id = UInt(0)) manager_xact_id = UInt(0))
} }
@ -1450,7 +1450,7 @@ class MemIOTileLinkIOConverter(qDepth: Int) extends TLModule with MIFParameters
dst = (if(dstIdBits > 0) tag_out(dst_off, tlClientXactIdBits + 1) else UInt(0)), dst = (if(dstIdBits > 0) tag_out(dst_off, tlClientXactIdBits + 1) else UInt(0)),
is_builtin_type = Bool(true), is_builtin_type = Bool(true),
g_type = Mux(data_from_rel, Grant.voluntaryAckType, Grant.putAckType), g_type = Mux(data_from_rel, Grant.voluntaryAckType, Grant.putAckType),
client_xact_id = tag_out >> UInt(1), client_xact_id = tag_out >> 1,
manager_xact_id = UInt(0)) manager_xact_id = UInt(0))
if(tlDataBits != mifDataBits || tlDataBeats != mifDataBeats) { if(tlDataBits != mifDataBits || tlDataBeats != mifDataBeats) {
@ -1619,7 +1619,7 @@ class MemIOTileLinkIOConverter(qDepth: Int) extends TLModule with MIFParameters
dst = (if(dstIdBits > 0) tag_in(dst_off, tlClientXactIdBits + 1) else UInt(0)), dst = (if(dstIdBits > 0) tag_in(dst_off, tlClientXactIdBits + 1) else UInt(0)),
is_builtin_type = tag_in(0), is_builtin_type = tag_in(0),
g_type = Mux(tag_in(0), Grant.getDataBlockType, UInt(0)), // TODO: Assumes MI or MEI protocol g_type = Mux(tag_in(0), Grant.getDataBlockType, UInt(0)), // TODO: Assumes MI or MEI protocol
client_xact_id = tag_in >> UInt(1), client_xact_id = tag_in >> 1,
manager_xact_id = UInt(0), manager_xact_id = UInt(0),
addr_beat = tl_cnt_in, addr_beat = tl_cnt_in,
data = tl_buf_in(tl_cnt_in)) data = tl_buf_in(tl_cnt_in))
@ -1651,7 +1651,7 @@ class MemIOTileLinkIOConverter(qDepth: Int) extends TLModule with MIFParameters
dst = (if(dstIdBits > 0) io.mem.resp.bits.tag(dst_off, tlClientXactIdBits + 1) else UInt(0)), dst = (if(dstIdBits > 0) io.mem.resp.bits.tag(dst_off, tlClientXactIdBits + 1) else UInt(0)),
is_builtin_type = io.mem.resp.bits.tag(0), is_builtin_type = io.mem.resp.bits.tag(0),
g_type = Mux(io.mem.resp.bits.tag(0), Grant.getDataBlockType, UInt(0)), // TODO: Assumes MI or MEI protocol g_type = Mux(io.mem.resp.bits.tag(0), Grant.getDataBlockType, UInt(0)), // TODO: Assumes MI or MEI protocol
client_xact_id = io.mem.resp.bits.tag >> UInt(1), client_xact_id = io.mem.resp.bits.tag >> 1,
manager_xact_id = UInt(0), manager_xact_id = UInt(0),
addr_beat = tl_cnt_in, addr_beat = tl_cnt_in,
data = io.mem.resp.bits.data) data = io.mem.resp.bits.data)