diff --git a/uncore/src/main/scala/cache.scala b/uncore/src/main/scala/cache.scala
index 6e5872c2..64966c20 100644
--- a/uncore/src/main/scala/cache.scala
+++ b/uncore/src/main/scala/cache.scala
@@ -87,7 +87,7 @@ class AMOALU extends CacheModule {
   val word = io.typ === MT_W || io.typ === MT_WU || // Logic minimization:
                io.typ === MT_B || io.typ === MT_BU
 
-  val mask = ~UInt(0,64) ^ (io.addr(2) << UInt(31))
+  val mask = ~UInt(0,64) ^ (io.addr(2) << 31)
   val adder_out = (io.lhs & mask).toUInt + (rhs & mask)
 
   val cmp_lhs  = Mux(word && !io.addr(2), io.lhs(31), io.lhs(63))
diff --git a/uncore/src/main/scala/ecc.scala b/uncore/src/main/scala/ecc.scala
index eb11c7b8..3f16901c 100644
--- a/uncore/src/main/scala/ecc.scala
+++ b/uncore/src/main/scala/ecc.scala
@@ -79,7 +79,7 @@ class SECCode extends Code
 
     private def swizzle(z: UInt) = Vec((1 to n).filter(i => !isPow2(i)).map(i => z(i-1))).toBits
     def uncorrected = swizzle(y)
-    def corrected = swizzle(((y.toUInt << UInt(1)) ^ UIntToOH(s)) >> UInt(1))
+    def corrected = swizzle(((y.toUInt << 1) ^ UIntToOH(s)) >> 1)
     def correctable = s.orR
     def uncorrectable = Bool(false)
   }
diff --git a/uncore/src/main/scala/htif.scala b/uncore/src/main/scala/htif.scala
index cb49d8d3..8aeba790 100644
--- a/uncore/src/main/scala/htif.scala
+++ b/uncore/src/main/scala/htif.scala
@@ -96,7 +96,7 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
     }
   }
 
-  val rx_word_count = (rx_count >> UInt(log2Up(short_request_bits/w)))
+  val rx_word_count = (rx_count >> log2Up(short_request_bits/w))
   val rx_word_done = io.host.in.valid && rx_count(log2Up(short_request_bits/w)-1,0).andR
   val packet_ram_depth = long_request_bits/short_request_bits-1
   val packet_ram = Mem(Bits(width = short_request_bits), packet_ram_depth)
@@ -173,7 +173,7 @@ class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
     packet_ram(Cat(cnt, ui))
   }.reverse.reduce(_##_)
 
-  val init_addr = addr.toUInt >> UInt(offsetBits-3)
+  val init_addr = addr.toUInt >> (offsetBits-3)
   io.mem.acquire.valid := state === state_mem_rreq || state === state_mem_wreq
   io.mem.acquire.bits := Mux(cmd === cmd_writemem, 
     PutBlock(
diff --git a/uncore/src/main/scala/tilelink.scala b/uncore/src/main/scala/tilelink.scala
index 3c6df452..d281744a 100644
--- a/uncore/src/main/scala/tilelink.scala
+++ b/uncore/src/main/scala/tilelink.scala
@@ -1112,7 +1112,7 @@ trait AppendsArbiterId extends TileLinkArbiterLike {
   def clientSourcedClientXactId(in: ClientSourcedWithId, id: Int) =
     Cat(in.client_xact_id, UInt(id, log2Up(arbN)))
   def managerSourcedClientXactId(in: ManagerSourcedWithId) = 
-    in.client_xact_id >> UInt(log2Up(arbN))
+    in.client_xact_id >> log2Up(arbN)
   def arbIdx(in: ManagerSourcedWithId) = in.client_xact_id(log2Up(arbN)-1,0).toUInt
 }
 
@@ -1378,7 +1378,7 @@ class NASTIMasterIOTileLinkIOConverter extends TLModule with NASTIParameters {
     dst = (if(dstIdBits > 0) io.nasti.r.bits.id(dst_off, tlClientXactIdBits + 1) else UInt(0)),
     is_builtin_type = io.nasti.r.bits.id(0),
     g_type = Mux(io.nasti.r.bits.id(0), Grant.getDataBlockType, UInt(0)), // TODO: Assumes MI or MEI protocol
-    client_xact_id = io.nasti.r.bits.id >> UInt(1),
+    client_xact_id = io.nasti.r.bits.id >> 1,
     manager_xact_id = UInt(0),
     addr_beat = tl_cnt_in,
     data = io.nasti.r.bits.data)
@@ -1389,7 +1389,7 @@ class NASTIMasterIOTileLinkIOConverter extends TLModule with NASTIParameters {
     dst = (if(dstIdBits > 0) io.nasti.b.bits.id(dst_off, tlClientXactIdBits + 1) else UInt(0)),
     is_builtin_type = Bool(true),
     g_type = Mux(io.nasti.b.bits.id(0), Grant.voluntaryAckType, Grant.putAckType),
-    client_xact_id = io.nasti.b.bits.id >> UInt(1),
+    client_xact_id = io.nasti.b.bits.id >> 1,
     manager_xact_id = UInt(0))
 }
 
@@ -1450,7 +1450,7 @@ class MemIOTileLinkIOConverter(qDepth: Int) extends TLModule with MIFParameters
     dst = (if(dstIdBits > 0) tag_out(dst_off, tlClientXactIdBits + 1) else UInt(0)),
     is_builtin_type = Bool(true),
     g_type = Mux(data_from_rel, Grant.voluntaryAckType, Grant.putAckType),
-    client_xact_id = tag_out >> UInt(1),
+    client_xact_id = tag_out >> 1,
     manager_xact_id = UInt(0))
 
   if(tlDataBits != mifDataBits || tlDataBeats != mifDataBeats) {
@@ -1619,7 +1619,7 @@ class MemIOTileLinkIOConverter(qDepth: Int) extends TLModule with MIFParameters
       dst = (if(dstIdBits > 0) tag_in(dst_off, tlClientXactIdBits + 1) else UInt(0)),
       is_builtin_type = tag_in(0),
       g_type = Mux(tag_in(0), Grant.getDataBlockType, UInt(0)), // TODO: Assumes MI or MEI protocol
-      client_xact_id = tag_in >> UInt(1),
+      client_xact_id = tag_in >> 1,
       manager_xact_id = UInt(0),
       addr_beat = tl_cnt_in,
       data = tl_buf_in(tl_cnt_in))
@@ -1651,7 +1651,7 @@ class MemIOTileLinkIOConverter(qDepth: Int) extends TLModule with MIFParameters
       dst = (if(dstIdBits > 0) io.mem.resp.bits.tag(dst_off, tlClientXactIdBits + 1) else UInt(0)),
       is_builtin_type = io.mem.resp.bits.tag(0),
       g_type = Mux(io.mem.resp.bits.tag(0), Grant.getDataBlockType, UInt(0)), // TODO: Assumes MI or MEI protocol
-      client_xact_id = io.mem.resp.bits.tag >> UInt(1),
+      client_xact_id = io.mem.resp.bits.tag >> 1,
       manager_xact_id = UInt(0),
       addr_beat = tl_cnt_in,
       data = io.mem.resp.bits.data)