riscv/rocket-chip
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Chisel3 compatibility: use >>Int instead of >>UInt

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The latter doesn't contract widths anymore.
This commit is contained in:
Andrew Waterman
2015-08-04 13:15:17 -07:00
parent fb718f03c1
commit 798ddeb5f5
4 changed files with 10 additions and 10 deletions
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2
uncore/src/main/scala/cache.scala
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@ -87,7 +87,7 @@ class AMOALU extends CacheModule {
val word = io.typ === MT_W || io.typ === MT_WU || // Logic minimization:
io.typ === MT_B || io.typ === MT_BU
val mask = ~UInt(0,64) ^ (io.addr(2) << UInt(31))
val mask = ~UInt(0,64) ^ (io.addr(2) << 31)
val adder_out = (io.lhs & mask).toUInt + (rhs & mask)
val cmp_lhs = Mux(word && !io.addr(2), io.lhs(31), io.lhs(63))