riscv/rocket-chip
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make mtvec configurable and writeable

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Howard Mao
2016-01-29 11:32:59 -08:00
parent 7937fbf074
commit 78579672d3
4 changed files with 8 additions and 7 deletions
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3
rocket/src/main/scala/rocket.scala
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@ -22,6 +22,7 @@ case object CoreInstBits extends Field[Int]
case object CoreDataBits extends Field[Int]
case object CoreDCacheReqTagBits extends Field[Int]
case object NCustomMRWCSRs extends Field[Int]
case object MtvecInit extends Field[BigInt]
trait HasCoreParameters extends HasAddrMapParameters {
implicit val p: Parameters
@ -50,6 +51,8 @@ trait HasCoreParameters extends HasAddrMapParameters {
else p(BuildRoCC).flatMap(_.csrs)
val nRoccCsrs = p(RoccNCSRs)
val nCores = p(HtifKey).nCores
val mtvecInit = p(MtvecInit)
val startAddr = mtvecInit + 0x100
// Print out log of committed instructions and their writeback values.
// Requires post-processing due to out-of-order writebacks.