From 78579672d3b8108c9962d5577f0c781164dc2647 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Fri, 29 Jan 2016 11:32:59 -0800
Subject: [PATCH] make mtvec configurable and writeable

---
 rocket/src/main/scala/csr.scala      | 6 ++++--
 rocket/src/main/scala/frontend.scala | 2 +-
 rocket/src/main/scala/package.scala  | 4 ----
 rocket/src/main/scala/rocket.scala   | 3 +++
 4 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index a1c277f9..62f81ff7 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -184,6 +184,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
   val cpuid = ((if (xLen == 32) BigInt(0) else BigInt(2)) << (xLen-2)) |
     isa_string.map(x => 1 << (x - 'A')).reduce(_|_)
   val impid = 1
+  val reg_mtvec = Reg(init = UInt(mtvecInit, xLen))
 
   val read_mapping = collection.mutable.LinkedHashMap[Int,Bits](
     CSRs.fflags -> (if (usingFPU) reg_fflags else UInt(0)),
@@ -201,7 +202,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
     CSRs.mstatus -> read_mstatus,
     CSRs.mtdeleg -> UInt(0),
     CSRs.mreset -> UInt(0),
-    CSRs.mtvec -> UInt(MTVEC),
+    CSRs.mtvec -> reg_mtvec,
     CSRs.miobase -> UInt(p(junctions.MMIOBase)),
     CSRs.mipi -> UInt(0),
     CSRs.mip -> reg_mip.toBits,
@@ -295,7 +296,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
   when (some_interrupt_pending) { reg_wfi := false }
 
   io.fatc := insn_sfence_vm
-  io.evec := Mux(io.exception || csr_xcpt, (reg_mstatus.prv << 6) + MTVEC,
+  io.evec := Mux(io.exception || csr_xcpt, (reg_mstatus.prv << 6) + reg_mtvec,
              Mux(maybe_insn_redirect_trap, reg_stvec.sextTo(vaddrBitsExtended),
              Mux(reg_mstatus.prv(1) || Bool(!p(UseVM)), reg_mepc, reg_sepc)))
   io.ptbr := reg_sptbr
@@ -427,6 +428,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
     when (decoded_addr(CSRs.mfromhost)){ when (reg_fromhost === UInt(0) || !host_csr_req_fire) { reg_fromhost := wdata } }
     when (decoded_addr(CSRs.mtohost))  { when (reg_tohost === UInt(0) || host_csr_req_fire) { reg_tohost := wdata } }
     when (decoded_addr(CSRs.stats))    { reg_stats := wdata(0) }
+    when (decoded_addr(CSRs.mtvec))    { reg_mtvec := wdata & ~UInt("b11") }
     if (usingVM) {
       when (decoded_addr(CSRs.sstatus)) {
         val new_sstatus = new SStatus().fromBits(wdata)
diff --git a/rocket/src/main/scala/frontend.scala b/rocket/src/main/scala/frontend.scala
index a5b9e9fa..96e7c2ec 100644
--- a/rocket/src/main/scala/frontend.scala
+++ b/rocket/src/main/scala/frontend.scala
@@ -42,7 +42,7 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
   val s1_pc = ~(~s1_pc_ | (coreInstBytes-1)) // discard PC LSBS (this propagates down the pipeline)
   val s1_same_block = Reg(Bool())
   val s2_valid = Reg(init=Bool(true))
-  val s2_pc = Reg(init=UInt(START_ADDR))
+  val s2_pc = Reg(init=UInt(startAddr))
   val s2_btb_resp_valid = Reg(init=Bool(false))
   val s2_btb_resp_bits = Reg(btb.io.resp.bits)
   val s2_xcpt_if = Reg(init=Bool(false))
diff --git a/rocket/src/main/scala/package.scala b/rocket/src/main/scala/package.scala
index e0b879ac..30368040 100644
--- a/rocket/src/main/scala/package.scala
+++ b/rocket/src/main/scala/package.scala
@@ -2,7 +2,3 @@
 
 package object rocket extends 
   rocket.constants.ScalarOpConstants
-{
-  val MTVEC = 0x100
-  val START_ADDR = MTVEC + 0x100
-}
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index 0e43d162..d9657095 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -22,6 +22,7 @@ case object CoreInstBits extends Field[Int]
 case object CoreDataBits extends Field[Int]
 case object CoreDCacheReqTagBits extends Field[Int]
 case object NCustomMRWCSRs extends Field[Int]
+case object MtvecInit extends Field[BigInt]
 
 trait HasCoreParameters extends HasAddrMapParameters {
   implicit val p: Parameters
@@ -50,6 +51,8 @@ trait HasCoreParameters extends HasAddrMapParameters {
     else p(BuildRoCC).flatMap(_.csrs)
   val nRoccCsrs = p(RoccNCSRs)
   val nCores = p(HtifKey).nCores
+  val mtvecInit = p(MtvecInit)
+  val startAddr = mtvecInit + 0x100
 
   // Print out log of committed instructions and their writeback values.
   // Requires post-processing due to out-of-order writebacks.