riscv/rocket-chip
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make mtvec configurable and writeable

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Howard Mao
2016-01-29 11:32:59 -08:00
parent 7937fbf074
commit 78579672d3
4 changed files with 8 additions and 7 deletions
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rocket/src/main/scala/frontend.scala
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@ -42,7 +42,7 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
val s1_pc = ~(~s1_pc_ | (coreInstBytes-1)) // discard PC LSBS (this propagates down the pipeline)
val s1_same_block = Reg(Bool())
val s2_valid = Reg(init=Bool(true))
val s2_pc = Reg(init=UInt(START_ADDR))
val s2_pc = Reg(init=UInt(startAddr))
val s2_btb_resp_valid = Reg(init=Bool(false))
val s2_btb_resp_bits = Reg(btb.io.resp.bits)
val s2_xcpt_if = Reg(init=Bool(false))