From 76af15a6ff88d3cf88133c0cc9c6d8e0c077eafd Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 9 Jun 2017 13:35:38 -0700 Subject: [PATCH] Fix FPU control bug for div/sqrt I was examining a WB-stage control signal instead of a MEM-stage control signal. I refactored the code to group the signals together, so that this sort of bug is less likely going forward. --- src/main/scala/tile/FPU.scala | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala index 7831d960..750bfc8d 100644 --- a/src/main/scala/tile/FPU.scala +++ b/src/main/scala/tile/FPU.scala @@ -754,15 +754,10 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { if (cfg.divSqrt) { val divSqrt_killed = Reg(Bool()) - makeDivSqrt(FType.S, wb_ctrl.singleOut) - fLen match { - case 32 => - case 64 => makeDivSqrt(FType.D, !wb_ctrl.singleOut) - } - - def makeDivSqrt(t: FType, en: Bool) = { + for (t <- floatTypes) { + val tag = !mem_ctrl.singleOut // TODO typeTag val divSqrt = Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) - divSqrt.io.inValid := en && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight + divSqrt.io.inValid := mem_reg_valid && tag === typeTag(t) && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)