riscv/rocket-chip
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fix problem introduced with verilog generation in vsim/fsim

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This commit is contained in:
Yunsup Lee
2014-09-04 09:49:57 -07:00
parent 6c6f5a3843
commit 763c57931b
5 changed files with 20 additions and 8 deletions
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4
Makefrag
View File

@@ -40,10 +40,6 @@ $(generated_dir)/$(FPGAMODEL)Mem.v: $(generated_dir)/$(FPGAMODEL).conf $(mem_gen
$(generated_dir)/memdessertMemDessert.v: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate MemDessert --backend v --targetDir $(generated_dir) --moduleNamePrefix memdessert"
# Generic Verilog
.PHONY: verilog
verilog: $(sim_vsrcs)
#--------------------------------------------------------------------
# DRAMSim2
#--------------------------------------------------------------------

4
fsim/Makefile
View File

@@ -15,11 +15,11 @@ mem_gen = $(base_dir)/fsim/fpga_mem_gen
sim_dir = .
output_dir = $(sim_dir)/output
include $(sim_dir)/Makefrag
include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag
include $(base_dir)/vsim/Makefrag-sim
all: $(simv)
clean:
rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)/*
rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)

8
fsim/Makefrag
View File

@@ -20,6 +20,14 @@ sim_csrcs = \
$(base_dir)/csrc/mm.cc \
$(base_dir)/csrc/mm_dramsim2.cc \
#--------------------------------------------------------------------
# Build Verilog
#--------------------------------------------------------------------
verilog: $(sim_vsrcs)
.PHONY: verilog
#--------------------------------------------------------------------
# Build rules
#--------------------------------------------------------------------

4
vsim/Makefile
View File

@@ -15,11 +15,11 @@ vlsi_mem_gen = $(base_dir)/vsim/vlsi_mem_gen
sim_dir = .
output_dir = $(sim_dir)/output
include $(sim_dir)/Makefrag
include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag
include $(base_dir)/vsim/Makefrag-sim
all: $(simv)
clean:
rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)/*
rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)

8
vsim/Makefrag
View File

@@ -19,6 +19,14 @@ sim_csrcs = \
$(base_dir)/csrc/mm.cc \
$(base_dir)/csrc/mm_dramsim2.cc \
#--------------------------------------------------------------------
# Build Verilog
#--------------------------------------------------------------------
verilog: $(sim_vsrcs)
.PHONY: verilog
#--------------------------------------------------------------------
# Build rules
#--------------------------------------------------------------------