From 763c57931b277f9eb0a92f5dc7cc2329d357a7d6 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Thu, 4 Sep 2014 09:49:57 -0700 Subject: [PATCH] fix problem introduced with verilog generation in vsim/fsim --- Makefrag | 4 ---- fsim/Makefile | 4 ++-- fsim/Makefrag | 8 ++++++++ vsim/Makefile | 4 ++-- vsim/Makefrag | 8 ++++++++ 5 files changed, 20 insertions(+), 8 deletions(-) diff --git a/Makefrag b/Makefrag index fd758617..14951cee 100644 --- a/Makefrag +++ b/Makefrag @@ -40,10 +40,6 @@ $(generated_dir)/$(FPGAMODEL)Mem.v: $(generated_dir)/$(FPGAMODEL).conf $(mem_gen $(generated_dir)/memdessertMemDessert.v: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate MemDessert --backend v --targetDir $(generated_dir) --moduleNamePrefix memdessert" -# Generic Verilog -.PHONY: verilog -verilog: $(sim_vsrcs) - #-------------------------------------------------------------------- # DRAMSim2 #-------------------------------------------------------------------- diff --git a/fsim/Makefile b/fsim/Makefile index 53a3a8d3..6c5da614 100644 --- a/fsim/Makefile +++ b/fsim/Makefile @@ -15,11 +15,11 @@ mem_gen = $(base_dir)/fsim/fpga_mem_gen sim_dir = . output_dir = $(sim_dir)/output -include $(sim_dir)/Makefrag include $(base_dir)/Makefrag +include $(sim_dir)/Makefrag include $(base_dir)/vsim/Makefrag-sim all: $(simv) clean: - rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)/* + rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir) diff --git a/fsim/Makefrag b/fsim/Makefrag index 325bdd21..2d79f8c2 100644 --- a/fsim/Makefrag +++ b/fsim/Makefrag @@ -20,6 +20,14 @@ sim_csrcs = \ $(base_dir)/csrc/mm.cc \ $(base_dir)/csrc/mm_dramsim2.cc \ +#-------------------------------------------------------------------- +# Build Verilog +#-------------------------------------------------------------------- + +verilog: $(sim_vsrcs) + +.PHONY: verilog + #-------------------------------------------------------------------- # Build rules #-------------------------------------------------------------------- diff --git a/vsim/Makefile b/vsim/Makefile index e427e5d4..ee403c08 100644 --- a/vsim/Makefile +++ b/vsim/Makefile @@ -15,11 +15,11 @@ vlsi_mem_gen = $(base_dir)/vsim/vlsi_mem_gen sim_dir = . output_dir = $(sim_dir)/output -include $(sim_dir)/Makefrag include $(base_dir)/Makefrag +include $(sim_dir)/Makefrag include $(base_dir)/vsim/Makefrag-sim all: $(simv) clean: - rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)/* + rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir) diff --git a/vsim/Makefrag b/vsim/Makefrag index fa27754f..93a19fd2 100644 --- a/vsim/Makefrag +++ b/vsim/Makefrag @@ -19,6 +19,14 @@ sim_csrcs = \ $(base_dir)/csrc/mm.cc \ $(base_dir)/csrc/mm_dramsim2.cc \ +#-------------------------------------------------------------------- +# Build Verilog +#-------------------------------------------------------------------- + +verilog: $(sim_vsrcs) + +.PHONY: verilog + #-------------------------------------------------------------------- # Build rules #--------------------------------------------------------------------