riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

fix problem introduced with verilog generation in vsim/fsim

Browse Source
This commit is contained in:
Yunsup Lee 2014-09-04 09:49:57 -07:00
parent 6c6f5a3843
commit 763c57931b
5 changed files with 20 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Makefrag
View File

@ -40,10 +40,6 @@ $(generated_dir)/$(FPGAMODEL)Mem.v: $(generated_dir)/$(FPGAMODEL).conf $(mem_gen
$(generated_dir)/memdessertMemDessert.v: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(generated_dir)/memdessertMemDessert.v: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate MemDessert --backend v --targetDir $(generated_dir) --moduleNamePrefix memdessert" cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate MemDessert --backend v --targetDir $(generated_dir) --moduleNamePrefix memdessert"
# Generic Verilog
.PHONY: verilog
verilog: $(sim_vsrcs)
#-------------------------------------------------------------------- #--------------------------------------------------------------------
# DRAMSim2 # DRAMSim2
#-------------------------------------------------------------------- #--------------------------------------------------------------------

4
fsim/Makefile
View File

@ -15,11 +15,11 @@ mem_gen = $(base_dir)/fsim/fpga_mem_gen
sim_dir = . sim_dir = .
output_dir = $(sim_dir)/output output_dir = $(sim_dir)/output
include $(sim_dir)/Makefrag
include $(base_dir)/Makefrag include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag
include $(base_dir)/vsim/Makefrag-sim include $(base_dir)/vsim/Makefrag-sim
all: $(simv) all: $(simv)
clean: clean:
rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)/* rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)

8
fsim/Makefrag
View File

@ -20,6 +20,14 @@ sim_csrcs = \
$(base_dir)/csrc/mm.cc \ $(base_dir)/csrc/mm.cc \
$(base_dir)/csrc/mm_dramsim2.cc \ $(base_dir)/csrc/mm_dramsim2.cc \
#--------------------------------------------------------------------
# Build Verilog
#--------------------------------------------------------------------
verilog: $(sim_vsrcs)
.PHONY: verilog
#-------------------------------------------------------------------- #--------------------------------------------------------------------
# Build rules # Build rules
#-------------------------------------------------------------------- #--------------------------------------------------------------------

4
vsim/Makefile
View File

@ -15,11 +15,11 @@ vlsi_mem_gen = $(base_dir)/vsim/vlsi_mem_gen
sim_dir = . sim_dir = .
output_dir = $(sim_dir)/output output_dir = $(sim_dir)/output
include $(sim_dir)/Makefrag
include $(base_dir)/Makefrag include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag
include $(base_dir)/vsim/Makefrag-sim include $(base_dir)/vsim/Makefrag-sim
all: $(simv) all: $(simv)
clean: clean:
rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)/* rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)

8
vsim/Makefrag
View File

@ -19,6 +19,14 @@ sim_csrcs = \
$(base_dir)/csrc/mm.cc \ $(base_dir)/csrc/mm.cc \
$(base_dir)/csrc/mm_dramsim2.cc \ $(base_dir)/csrc/mm_dramsim2.cc \
#--------------------------------------------------------------------
# Build Verilog
#--------------------------------------------------------------------
verilog: $(sim_vsrcs)
.PHONY: verilog
#-------------------------------------------------------------------- #--------------------------------------------------------------------
# Build rules # Build rules
#-------------------------------------------------------------------- #--------------------------------------------------------------------