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fix problem introduced with verilog generation in vsim/fsim

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This commit is contained in:
Yunsup Lee
2014-09-04 09:49:57 -07:00
parent 6c6f5a3843
commit 763c57931b
5 changed files with 20 additions and 8 deletions
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8
vsim/Makefrag
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@ -19,6 +19,14 @@ sim_csrcs = \
$(base_dir)/csrc/mm.cc \
$(base_dir)/csrc/mm_dramsim2.cc \
#--------------------------------------------------------------------
# Build Verilog
#--------------------------------------------------------------------
verilog: $(sim_vsrcs)
.PHONY: verilog
#--------------------------------------------------------------------
# Build rules
#--------------------------------------------------------------------