fix problem introduced with verilog generation in vsim/fsim

fsim/Makefrag

@@ -20,6 +20,14 @@ sim_csrcs = \
 	$(base_dir)/csrc/mm.cc \
 	$(base_dir)/csrc/mm_dramsim2.cc \
 
+#--------------------------------------------------------------------
+# Build Verilog
+#--------------------------------------------------------------------
+
+verilog: $(sim_vsrcs)
+
+.PHONY: verilog
+
 #--------------------------------------------------------------------
 # Build rules
 #--------------------------------------------------------------------