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fix problem introduced with verilog generation in vsim/fsim

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This commit is contained in:
Yunsup Lee
2014-09-04 09:49:57 -07:00
parent 6c6f5a3843
commit 763c57931b
5 changed files with 20 additions and 8 deletions
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4
fsim/Makefile
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@ -15,11 +15,11 @@ mem_gen = $(base_dir)/fsim/fpga_mem_gen
sim_dir = .
output_dir = $(sim_dir)/output
include $(sim_dir)/Makefrag
include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag
include $(base_dir)/vsim/Makefrag-sim
all: $(simv)
clean:
rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)/*
rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)