riscv/rocket-chip
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fix problem introduced with verilog generation in vsim/fsim

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This commit is contained in:
Yunsup Lee
2014-09-04 09:49:57 -07:00
parent 6c6f5a3843
commit 763c57931b
5 changed files with 20 additions and 8 deletions
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4
Makefrag
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@ -40,10 +40,6 @@ $(generated_dir)/$(FPGAMODEL)Mem.v: $(generated_dir)/$(FPGAMODEL).conf $(mem_gen
$(generated_dir)/memdessertMemDessert.v: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate MemDessert --backend v --targetDir $(generated_dir) --moduleNamePrefix memdessert"
# Generic Verilog
.PHONY: verilog
verilog: $(sim_vsrcs)
#--------------------------------------------------------------------
# DRAMSim2
#--------------------------------------------------------------------