riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Set xPIE=1 on xRET

Browse Source 
We were setting xPIE=0 instead.  This is a benign bug, but still a bug.
This commit is contained in:
Andrew Waterman 2017-02-01 22:40:01 -08:00 committed by Andrew Waterman
parent b2ee5e7d38
commit 75edf42323
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/rocket/csr.scala
View File

@ -478,7 +478,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
when (insn_ret) {
when (Bool(usingVM) && !csr_addr_priv(1)) {
when (reg_mstatus.spp.toBool) { reg_mstatus.sie := reg_mstatus.spie }
reg_mstatus.spie := false
reg_mstatus.spie := true
reg_mstatus.spp := PRV.U
new_prv := reg_mstatus.spp
}.elsewhen (csr_debug) {
@ -487,7 +487,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
}.otherwise {
when (reg_mstatus.mpp(1)) { reg_mstatus.mie := reg_mstatus.mpie }
.elsewhen (Bool(usingVM) && reg_mstatus.mpp(0)) { reg_mstatus.sie := reg_mstatus.mpie }
reg_mstatus.mpie := false
reg_mstatus.mpie := true
reg_mstatus.mpp := legalizePrivilege(PRV.U)
new_prv := reg_mstatus.mpp
}