From 75edf42323b38f7da5f5ddff296eccebdc5113bf Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 1 Feb 2017 22:40:01 -0800 Subject: [PATCH] Set xPIE=1 on xRET We were setting xPIE=0 instead. This is a benign bug, but still a bug. --- src/main/scala/rocket/csr.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/csr.scala b/src/main/scala/rocket/csr.scala index 8fc83ab3..cca442d4 100644 --- a/src/main/scala/rocket/csr.scala +++ b/src/main/scala/rocket/csr.scala @@ -478,7 +478,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) when (insn_ret) { when (Bool(usingVM) && !csr_addr_priv(1)) { when (reg_mstatus.spp.toBool) { reg_mstatus.sie := reg_mstatus.spie } - reg_mstatus.spie := false + reg_mstatus.spie := true reg_mstatus.spp := PRV.U new_prv := reg_mstatus.spp }.elsewhen (csr_debug) { @@ -487,7 +487,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) }.otherwise { when (reg_mstatus.mpp(1)) { reg_mstatus.mie := reg_mstatus.mpie } .elsewhen (Bool(usingVM) && reg_mstatus.mpp(0)) { reg_mstatus.sie := reg_mstatus.mpie } - reg_mstatus.mpie := false + reg_mstatus.mpie := true reg_mstatus.mpp := legalizePrivilege(PRV.U) new_prv := reg_mstatus.mpp }