riscv/rocket-chip
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Make I vs. D a static property of TLB, not an input pin

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The microarchitecture doesn't really support unified TLBs, so don't fake it.
This commit is contained in:
Andrew Waterman
2017-08-08 11:52:35 -07:00
parent 6d1d285464
commit 74d309c18e
4 changed files with 5 additions and 8 deletions
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3
src/main/scala/rocket/Frontend.scala
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@ -82,7 +82,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes)
val fetchBytes = coreInstBytes * fetchWidth
val tlb = Module(new TLB(log2Ceil(fetchBytes), nTLBEntries))
val tlb = Module(new TLB(true, log2Ceil(fetchBytes), nTLBEntries))
val fq = withReset(reset || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 5, flow = true)) }
val s0_valid = io.cpu.req.valid || !fq.io.mask(fq.io.mask.getWidth-3)
@ -130,7 +130,6 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
tlb.io.req.valid := !s2_replay
tlb.io.req.bits.vaddr := s1_pc
tlb.io.req.bits.passthrough := Bool(false)
tlb.io.req.bits.instruction := Bool(true)
tlb.io.req.bits.sfence := io.cpu.sfence
tlb.io.req.bits.size := log2Ceil(coreInstBytes*fetchWidth)