From 74d309c18e0f2eea6bae9a7a367e21281ddcfc23 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 8 Aug 2017 11:52:35 -0700 Subject: [PATCH] Make I vs. D a static property of TLB, not an input pin The microarchitecture doesn't really support unified TLBs, so don't fake it. --- src/main/scala/rocket/DCache.scala | 3 +-- src/main/scala/rocket/Frontend.scala | 3 +-- src/main/scala/rocket/NBDcache.scala | 3 +-- src/main/scala/rocket/TLB.scala | 4 ++-- 4 files changed, 5 insertions(+), 8 deletions(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index e83796ea..9429438c 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -144,7 +144,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { when (!metaArb.io.in(7).ready) { io.cpu.req.ready := false } // address translation - val tlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries)) + val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), nTLBEntries)) io.ptw <> tlb.io.ptw tlb.io.req.valid := s1_valid && !io.cpu.s1_kill && (s1_readwrite || s1_sfence) tlb.io.req.bits.sfence.valid := s1_sfence @@ -154,7 +154,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { tlb.io.req.bits.sfence.bits.addr := s1_req.addr tlb.io.req.bits.passthrough := s1_req.phys tlb.io.req.bits.vaddr := s1_req.addr - tlb.io.req.bits.instruction := false tlb.io.req.bits.size := s1_req.typ tlb.io.req.bits.cmd := s1_req.cmd when (!tlb.io.req.ready && !tlb.io.ptw.resp.valid && !io.cpu.req.bits.phys) { io.cpu.req.ready := false } diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala index b4088bfe..465e521d 100644 --- a/src/main/scala/rocket/Frontend.scala +++ b/src/main/scala/rocket/Frontend.scala @@ -82,7 +82,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes) val fetchBytes = coreInstBytes * fetchWidth - val tlb = Module(new TLB(log2Ceil(fetchBytes), nTLBEntries)) + val tlb = Module(new TLB(true, log2Ceil(fetchBytes), nTLBEntries)) val fq = withReset(reset || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 5, flow = true)) } val s0_valid = io.cpu.req.valid || !fq.io.mask(fq.io.mask.getWidth-3) @@ -130,7 +130,6 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) tlb.io.req.valid := !s2_replay tlb.io.req.bits.vaddr := s1_pc tlb.io.req.bits.passthrough := Bool(false) - tlb.io.req.bits.instruction := Bool(true) tlb.io.req.bits.sfence := io.cpu.sfence tlb.io.req.bits.size := log2Ceil(coreInstBytes*fetchWidth) diff --git a/src/main/scala/rocket/NBDcache.scala b/src/main/scala/rocket/NBDcache.scala index fd96ec7f..8d9899d4 100644 --- a/src/main/scala/rocket/NBDcache.scala +++ b/src/main/scala/rocket/NBDcache.scala @@ -700,7 +700,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule // check for unsupported operations assert(!s1_valid || !s1_req.cmd.isOneOf(M_PWR)) - val dtlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries)) + val dtlb = Module(new TLB(false, log2Ceil(coreDataBytes), nTLBEntries)) io.ptw <> dtlb.io.ptw dtlb.io.req.valid := s1_valid && !io.cpu.s1_kill && (s1_readwrite || s1_sfence) dtlb.io.req.bits.sfence.valid := s1_sfence @@ -710,7 +710,6 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule dtlb.io.req.bits.sfence.bits.asid := io.cpu.s1_data.data dtlb.io.req.bits.passthrough := s1_req.phys dtlb.io.req.bits.vaddr := s1_req.addr - dtlb.io.req.bits.instruction := Bool(false) dtlb.io.req.bits.size := s1_req.typ dtlb.io.req.bits.cmd := s1_req.cmd when (!dtlb.io.req.ready && !io.cpu.req.bits.phys) { io.cpu.req.ready := Bool(false) } diff --git a/src/main/scala/rocket/TLB.scala b/src/main/scala/rocket/TLB.scala index 14b65732..3ad59c4f 100644 --- a/src/main/scala/rocket/TLB.scala +++ b/src/main/scala/rocket/TLB.scala @@ -52,7 +52,7 @@ class TLBResp(implicit p: Parameters) extends CoreBundle()(p) { val prefetchable = Bool() } -class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { +class TLB(instruction: Boolean, lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = new Bundle { val req = Decoupled(new TLBReq(lgMaxSize)).flip val resp = new TLBResp().asOutput @@ -92,7 +92,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters val r_refill_waddr = Reg(UInt(width = log2Ceil(normalEntries))) val r_req = Reg(new TLBReq(lgMaxSize)) - val priv = Mux(io.req.bits.instruction, io.ptw.status.prv, io.ptw.status.dprv) + val priv = if (instruction) io.ptw.status.prv else io.ptw.status.dprv val priv_s = priv(0) val priv_uses_vm = priv <= PRV.S val vm_enabled = Bool(usingVM) && io.ptw.ptbr.mode(io.ptw.ptbr.mode.getWidth-1) && priv_uses_vm && !io.req.bits.passthrough