riscv/rocket-chip
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Make I vs. D a static property of TLB, not an input pin

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The microarchitecture doesn't really support unified TLBs, so don't fake it.
This commit is contained in:
Andrew Waterman
2017-08-08 11:52:35 -07:00
parent 6d1d285464
commit 74d309c18e
4 changed files with 5 additions and 8 deletions
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3
src/main/scala/rocket/DCache.scala
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@ -144,7 +144,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
when (!metaArb.io.in(7).ready) { io.cpu.req.ready := false }
// address translation
val tlb = Module(new TLB(log2Ceil(coreDataBytes), nTLBEntries))
val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), nTLBEntries))
io.ptw <> tlb.io.ptw
tlb.io.req.valid := s1_valid && !io.cpu.s1_kill && (s1_readwrite || s1_sfence)
tlb.io.req.bits.sfence.valid := s1_sfence
@ -154,7 +154,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
tlb.io.req.bits.sfence.bits.addr := s1_req.addr
tlb.io.req.bits.passthrough := s1_req.phys
tlb.io.req.bits.vaddr := s1_req.addr
tlb.io.req.bits.instruction := false
tlb.io.req.bits.size := s1_req.typ
tlb.io.req.bits.cmd := s1_req.cmd
when (!tlb.io.req.ready && !tlb.io.ptw.resp.valid && !io.cpu.req.bits.phys) { io.cpu.req.ready := false }