Refactor Tile to use cake pattern (#502)
* [rocket] Refactor Tile into cake pattern with traits * [rocket] cacheDataBits &etc in HasCoreParameters * [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters * [rocket] frontend and icache now diplomatic * [rocket] file name capitalization * [rocket] re-add hook for inserting externally-defined Cores * [rocket] add FPUCoreIO * [groundtest] move TL1 Config instances to where they are used * [unittest] remove legacy unit tests * [groundtest] remove legacy device tests
This commit is contained in:
Henry Cook
GitHub
@ -4,161 +4,72 @@
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package rocket
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import Chisel._
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import config._
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import coreplex._
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import diplomacy._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.util.{CacheName, CacheBlockBytes}
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import uncore.converters._
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import uncore.devices._
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import uncore.tilelink2._
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import util._
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import config._
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import scala.collection.mutable.ListBuffer
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case object BuildRoCC extends Field[Seq[RoccParameters]]
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class RocketTile(val c: RocketConfig)(implicit p: Parameters) extends BaseTile()(p)
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with CanHaveLegacyRoccs // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache
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with CanHaveScratchpad { // implies CanHavePTW with HasHellaCache with HasICacheFrontend
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case class RoccParameters(
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opcodes: OpcodeSet,
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generator: Parameters => RoCC,
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nMemChannels: Int = 0,
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nPTWPorts : Int = 0,
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useFPU: Boolean = false)
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nDCachePorts += 1 // core TODO dcachePorts += () => module.core.io.dmem ??
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class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
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val coreParams = p.alterPartial {
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case TLCacheEdge => cachedOut.edgesOut(0)
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}
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val dcacheParams = coreParams.alterPartial({
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case CacheName => CacheName("L1D")
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case TLId => "L1toL2"
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})
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val icacheParams = coreParams.alterPartial({
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case CacheName => CacheName("L1I")
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case TLId => "L1toL2"
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})
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override lazy val module = new RocketTileModule(this)
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}
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val slaveNode = if (p(DataScratchpadSize) == 0) None else Some(TLInputNode())
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val scratch = if (p(DataScratchpadSize) == 0) None else Some(LazyModule(new ScratchpadSlavePort()(dcacheParams)))
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def findScratch() = scratch.map { s =>
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val finalNode = uncachedOut.edgesOut(0).manager.managers.find(_.nodePath.last == s.node)
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require (finalNode.isDefined, "Could not find the scratch pad; not reachable via icache?")
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require (finalNode.get.address.size == 1, "Scratchpad address space was fragmented!")
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finalNode.get.address(0)
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class RocketTileBundle(outer: RocketTile) extends BaseTileBundle(outer)
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with CanHaveScratchpadBundle
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class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => new RocketTileBundle(outer))
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with CanHaveLegacyRoccsModule
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with CanHaveScratchpadModule {
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val core = Module(p(BuildCore)(outer.c, outer.p))
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core.io.interrupts := io.interrupts
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core.io.hartid := io.hartid
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outer.frontend.module.io.cpu <> core.io.imem
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outer.frontend.module.io.resetVector := io.resetVector
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dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ??
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fpuOpt foreach { fpu => core.io.fpu <> fpu.io }
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ptwOpt foreach { ptw => core.io.ptw <> ptw.io.dpath }
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outer.legacyRocc foreach { lr =>
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lr.module.io.core.cmd <> core.io.rocc.cmd
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lr.module.io.core.exception := core.io.rocc.exception
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core.io.rocc.resp <> lr.module.io.core.resp
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core.io.rocc.busy := lr.module.io.core.busy
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core.io.rocc.interrupt := lr.module.io.core.interrupt
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}
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val dcache = HellaCache(p(DCacheKey), findScratch)(dcacheParams)
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val frontend = LazyModule(new Frontend()(icacheParams))
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val ucLegacy = LazyModule(new TLLegacy()(icacheParams))
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val tileXbar = LazyModule(new TLXbar)
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tileXbar.node := TLHintHandler()(ucLegacy.node)
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tileXbar.node := frontend.node
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// TODO figure out how to move the below into their respective mix-ins
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require(dcachePorts.size == core.dcacheArbPorts)
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dcacheArb.io.requestor <> dcachePorts
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ptwOpt foreach { ptw => ptw.io.requestor <> ptwPorts }
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}
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val cachedOut = TLOutputNode()
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val uncachedOut = TLOutputNode()
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cachedOut := dcache.node
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uncachedOut := tileXbar.node
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val masterNodes = List(cachedOut, uncachedOut)
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class AsyncRocketTile(c: RocketConfig)(implicit p: Parameters) extends LazyModule {
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val rocket = LazyModule(new RocketTile(c))
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(slaveNode zip scratch) foreach { case (node, lm) => lm.node := TLFragmenter(p(XLen)/8, p(CacheBlockBytes))(node) }
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val masterNodes = rocket.masterNodes.map(_ => TLAsyncOutputNode())
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val slaveNode = rocket.slaveNode.map(_ => TLAsyncInputNode())
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(rocket.masterNodes zip masterNodes) foreach { case (r,n) => n := TLAsyncCrossingSource()(r) }
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(rocket.slaveNode zip slaveNode) foreach { case (r,n) => r := TLAsyncCrossingSink()(n) }
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val cached = cachedOut.bundleOut
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val uncached = uncachedOut.bundleOut
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val master = masterNodes.map(_.bundleOut)
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val slave = slaveNode.map(_.bundleIn)
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val hartid = UInt(INPUT, p(XLen))
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val interrupts = new TileInterrupts()(coreParams).asInput
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val interrupts = new TileInterrupts()(p).asInput
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val resetVector = UInt(INPUT, p(XLen))
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}
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val buildRocc = p(BuildRoCC)
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val usingRocc = !buildRocc.isEmpty
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val nRocc = buildRocc.size
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val nFPUPorts = buildRocc.filter(_.useFPU).size
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val core = Module(new Rocket()(dcacheParams))
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val ptwPorts = ListBuffer(frontend.module.io.ptw, dcache.module.io.ptw)
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val dcPorts = ListBuffer(core.io.dmem)
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val uncachedArbPorts = ListBuffer[ClientUncachedTileLinkIO]()
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core.io.interrupts := io.interrupts
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core.io.hartid := io.hartid
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frontend.module.io.cpu <> core.io.imem
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frontend.module.io.resetVector := io.resetVector
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val fpuOpt = p(FPUKey).map(cfg => Module(new FPU(cfg)(coreParams)))
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fpuOpt.foreach(fpu => core.io.fpu <> fpu.io)
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if (usingRocc) {
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val respArb = Module(new RRArbiter(new RoCCResponse()(coreParams), nRocc))
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core.io.rocc.resp <> respArb.io.out
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val roccOpcodes = buildRocc.map(_.opcodes)
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val cmdRouter = Module(new RoccCommandRouter(roccOpcodes)(coreParams))
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cmdRouter.io.in <> core.io.rocc.cmd
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val roccs = buildRocc.zipWithIndex.map { case (accelParams, i) =>
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val rocc = accelParams.generator(dcacheParams.alterPartial({
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case RoccNMemChannels => accelParams.nMemChannels
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case RoccNPTWPorts => accelParams.nPTWPorts
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}))
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val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
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rocc.io.cmd <> cmdRouter.io.out(i)
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rocc.io.exception := core.io.rocc.exception
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dcIF.io.requestor <> rocc.io.mem
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dcPorts += dcIF.io.cache
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uncachedArbPorts += rocc.io.autl
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rocc
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}
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if (nFPUPorts > 0) {
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fpuOpt.foreach { fpu =>
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val fpArb = Module(new InOrderArbiter(new FPInput()(coreParams), new FPResult()(coreParams), nFPUPorts))
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val fp_roccs = roccs.zip(buildRocc)
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.filter { case (_, params) => params.useFPU }
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.map { case (rocc, _) => rocc.io }
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fpArb.io.in_req <> fp_roccs.map(_.fpu_req)
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fp_roccs.zip(fpArb.io.in_resp).foreach {
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case (rocc, fpu_resp) => rocc.fpu_resp <> fpu_resp
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}
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fpu.io.cp_req <> fpArb.io.out_req
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fpArb.io.out_resp <> fpu.io.cp_resp
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}
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}
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core.io.rocc.busy := cmdRouter.io.busy || roccs.map(_.io.busy).reduce(_ || _)
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core.io.rocc.interrupt := roccs.map(_.io.interrupt).reduce(_ || _)
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respArb.io.in <> roccs.map(rocc => Queue(rocc.io.resp))
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ptwPorts ++= roccs.flatMap(_.io.ptw)
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uncachedArbPorts ++= roccs.flatMap(_.io.utl) // TODO no difference between io.autl and io.utl for now
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val uncachedArb = Module(new ClientUncachedTileLinkIOArbiter(uncachedArbPorts.size)(icacheParams))
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uncachedArb.io.in <> uncachedArbPorts
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ucLegacy.module.io.legacy <> uncachedArb.io.out
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} else {
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ucLegacy.module.io.legacy.acquire.valid := Bool(false)
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ucLegacy.module.io.legacy.grant.ready := Bool(false)
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}
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if (p(UseVM)) {
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val ptw = Module(new PTW(ptwPorts.size)(dcacheParams))
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ptw.io.requestor <> ptwPorts
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ptw.io.mem +=: dcPorts
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core.io.ptw <> ptw.io.dpath
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}
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scratch.foreach { lm => lm.module.io.dmem +=: dcPorts }
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require(dcPorts.size == core.dcacheArbPorts)
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val dcArb = Module(new HellaCacheArbiter(dcPorts.size)(dcacheParams))
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dcArb.io.requestor <> dcPorts
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dcache.module.io.cpu <> dcArb.io.mem
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if (nFPUPorts == 0) {
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fpuOpt.foreach { fpu =>
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fpu.io.cp_req.valid := Bool(false)
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fpu.io.cp_resp.ready := Bool(false)
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}
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}
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rocket.module.io.interrupts := ShiftRegister(io.interrupts, 3)
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// signals that do not change:
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rocket.module.io.hartid := io.hartid
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rocket.module.io.resetVector := io.resetVector
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}
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}
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