74b6a8d02b
* [rocket] Refactor Tile into cake pattern with traits * [rocket] cacheDataBits &etc in HasCoreParameters * [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters * [rocket] frontend and icache now diplomatic * [rocket] file name capitalization * [rocket] re-add hook for inserting externally-defined Cores * [rocket] add FPUCoreIO * [groundtest] move TL1 Config instances to where they are used * [unittest] remove legacy unit tests * [groundtest] remove legacy device tests
76 lines
2.8 KiB
Scala
76 lines
2.8 KiB
Scala
// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package rocket
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import Chisel._
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import config._
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import coreplex._
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import diplomacy._
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import uncore.converters._
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import uncore.devices._
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import uncore.tilelink2._
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import util._
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class RocketTile(val c: RocketConfig)(implicit p: Parameters) extends BaseTile()(p)
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with CanHaveLegacyRoccs // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache
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with CanHaveScratchpad { // implies CanHavePTW with HasHellaCache with HasICacheFrontend
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nDCachePorts += 1 // core TODO dcachePorts += () => module.core.io.dmem ??
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override lazy val module = new RocketTileModule(this)
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}
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class RocketTileBundle(outer: RocketTile) extends BaseTileBundle(outer)
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with CanHaveScratchpadBundle
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class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => new RocketTileBundle(outer))
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with CanHaveLegacyRoccsModule
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with CanHaveScratchpadModule {
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val core = Module(p(BuildCore)(outer.c, outer.p))
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core.io.interrupts := io.interrupts
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core.io.hartid := io.hartid
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outer.frontend.module.io.cpu <> core.io.imem
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outer.frontend.module.io.resetVector := io.resetVector
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dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ??
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fpuOpt foreach { fpu => core.io.fpu <> fpu.io }
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ptwOpt foreach { ptw => core.io.ptw <> ptw.io.dpath }
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outer.legacyRocc foreach { lr =>
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lr.module.io.core.cmd <> core.io.rocc.cmd
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lr.module.io.core.exception := core.io.rocc.exception
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core.io.rocc.resp <> lr.module.io.core.resp
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core.io.rocc.busy := lr.module.io.core.busy
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core.io.rocc.interrupt := lr.module.io.core.interrupt
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}
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// TODO figure out how to move the below into their respective mix-ins
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require(dcachePorts.size == core.dcacheArbPorts)
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dcacheArb.io.requestor <> dcachePorts
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ptwOpt foreach { ptw => ptw.io.requestor <> ptwPorts }
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}
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class AsyncRocketTile(c: RocketConfig)(implicit p: Parameters) extends LazyModule {
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val rocket = LazyModule(new RocketTile(c))
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val masterNodes = rocket.masterNodes.map(_ => TLAsyncOutputNode())
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val slaveNode = rocket.slaveNode.map(_ => TLAsyncInputNode())
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(rocket.masterNodes zip masterNodes) foreach { case (r,n) => n := TLAsyncCrossingSource()(r) }
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(rocket.slaveNode zip slaveNode) foreach { case (r,n) => r := TLAsyncCrossingSink()(n) }
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val master = masterNodes.map(_.bundleOut)
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val slave = slaveNode.map(_.bundleIn)
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val hartid = UInt(INPUT, p(XLen))
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val interrupts = new TileInterrupts()(p).asInput
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val resetVector = UInt(INPUT, p(XLen))
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}
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rocket.module.io.interrupts := ShiftRegister(io.interrupts, 3)
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// signals that do not change:
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rocket.module.io.hartid := io.hartid
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rocket.module.io.resetVector := io.resetVector
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}
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}
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