Refactor Tile to use cake pattern (#502)
* [rocket] Refactor Tile into cake pattern with traits * [rocket] cacheDataBits &etc in HasCoreParameters * [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters * [rocket] frontend and icache now diplomatic * [rocket] file name capitalization * [rocket] re-add hook for inserting externally-defined Cores * [rocket] add FPUCoreIO * [groundtest] move TL1 Config instances to where they are used * [unittest] remove legacy unit tests * [groundtest] remove legacy device tests
This commit is contained in:
Henry Cook
GitHub
93
src/main/scala/rocket/Core.scala
Normal file
93
src/main/scala/rocket/Core.scala
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@ -0,0 +1,93 @@
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// See LICENSE.SiFive for license details.
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package rocket
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import Chisel._
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import config._
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import uncore.tilelink2.TLEdgeOut
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import uncore.util.{CacheName, CacheBlockBytes}
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import util._
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case object BuildCore extends Field[(RocketConfig, Parameters) => CoreModule with HasCoreIO]
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case object SharedMemoryTLEdge extends Field[TLEdgeOut]
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trait HasCoreParameters {
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implicit val p: Parameters
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val xLen = p(XLen)
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val fLen = xLen // TODO relax this
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val usingVM = p(UseVM)
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val usingUser = p(UseUser) || usingVM
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val usingDebug = p(UseDebug)
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val usingMulDiv = p(MulDivKey).nonEmpty
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val usingFPU = p(FPUKey).nonEmpty
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val usingAtomics = p(UseAtomics)
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val usingCompressed = p(UseCompressed)
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val usingRoCC = !p(BuildRoCC).isEmpty
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val fastLoadWord = p(FastLoadWord)
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val fastLoadByte = p(FastLoadByte)
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val fastJAL = p(FastJAL)
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val nBreakpoints = p(NBreakpoints)
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val nPerfCounters = p(NPerfCounters)
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val nPerfEvents = p(NPerfEvents)
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val usingDataScratchpad = p(DataScratchpadSize) > 0
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val retireWidth = p(RetireWidth)
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val fetchWidth = p(FetchWidth)
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val coreInstBits = p(CoreInstBits)
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val coreInstBytes = coreInstBits/8
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val coreDataBits = xLen
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val coreDataBytes = coreDataBits/8
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val dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size
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val coreDCacheReqTagBits = 6
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val dcacheReqTagBits = coreDCacheReqTagBits + log2Ceil(dcacheArbPorts)
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def pgIdxBits = 12
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def pgLevelBits = 10 - log2Ceil(xLen / 32)
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def vaddrBits = pgIdxBits + pgLevels * pgLevelBits
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val paddrBits = p(PAddrBits)
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def ppnBits = paddrBits - pgIdxBits
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def vpnBits = vaddrBits - pgIdxBits
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val pgLevels = p(PgLevels)
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val asIdBits = p(ASIdBits)
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val vpnBitsExtended = vpnBits + (vaddrBits < xLen).toInt
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val vaddrBitsExtended = vpnBitsExtended + pgIdxBits
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val coreMaxAddrBits = paddrBits max vaddrBitsExtended
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val nCustomMrwCsrs = p(NCustomMRWCSRs)
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// fetchWidth doubled, but coreInstBytes halved, for RVC
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val decodeWidth = fetchWidth / (if (usingCompressed) 2 else 1)
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// Print out log of committed instructions and their writeback values.
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// Requires post-processing due to out-of-order writebacks.
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val enableCommitLog = false
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val maxPAddrBits = xLen match {
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case 32 => 34
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case 64 => 50
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}
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require(paddrBits <= maxPAddrBits)
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require(!fastLoadByte || fastLoadWord)
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}
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abstract class CoreModule(implicit val p: Parameters) extends Module
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with HasCoreParameters
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abstract class CoreBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasCoreParameters
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trait HasCoreIO {
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implicit val p: Parameters
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val io = new Bundle {
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val interrupts = new TileInterrupts().asInput
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val hartid = UInt(INPUT, p(XLen))
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val imem = new FrontendIO()(p.alterPartial({case CacheName => CacheName("L1I") }))
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val dmem = new HellaCacheIO()(p.alterPartial({ case CacheName => CacheName("L1D") }))
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val ptw = new DatapathPTWIO().flip
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val fpu = new FPUCoreIO().flip
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val rocc = new RoCCCoreIO().flip
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}
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}
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@ -38,7 +38,7 @@ class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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}
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}
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class DCache(cfg: DCacheConfig, val scratch: () => Option[AddressSet])(implicit p: Parameters) extends HellaCache(cfg)(p) {
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class DCache(cfg: DCacheConfig, val scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) extends HellaCache(cfg)(p) {
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override lazy val module = new DCacheModule(this)
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}
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@ -149,7 +149,7 @@ class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
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sigs zip decoder map {case(s,d) => s := d}
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}
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class FPUIO(implicit p: Parameters) extends CoreBundle {
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class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
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val inst = Bits(INPUT, 32)
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val fromint_data = Bits(INPUT, xLen)
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@ -174,7 +174,9 @@ class FPUIO(implicit p: Parameters) extends CoreBundle {
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val sboard_set = Bool(OUTPUT)
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val sboard_clr = Bool(OUTPUT)
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val sboard_clra = UInt(OUTPUT, 5)
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}
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class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
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val cp_req = Decoupled(new FPInput()).flip //cp doesn't pay attn to kill sigs
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val cp_resp = Decoupled(new FPResult())
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}
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@ -729,3 +731,14 @@ class FPU(cfg: FPUConfig)(implicit p: Parameters) extends FPUModule()(p) {
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when (ex_ctrl.div || ex_ctrl.sqrt) { io.illegal_rm := true }
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}
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}
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/** Mix-ins for constructing tiles that may have an FPU external to the core pipeline */
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trait CanHaveSharedFPU {
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implicit val p: Parameters
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}
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trait CanHaveSharedFPUModule {
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val outer: CanHaveSharedFPU
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val fpuOpt = outer.p(FPUKey).map(cfg => Module(new FPU(cfg)(outer.p)))
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// TODO fpArb could go here instead of inside LegacyRoccComplex
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}
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@ -5,8 +5,10 @@ package rocket
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import Chisel._
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import config._
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import coreplex._
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import diplomacy._
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import uncore.tilelink2._
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import uncore.util.CacheName
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import util._
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import Chisel.ImplicitConversions._
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@ -149,3 +151,23 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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io.cpu.resp.bits.btb.valid := s2_btb_resp_valid
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io.cpu.resp.bits.btb.bits := s2_btb_resp_bits
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}
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/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
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trait HasICacheFrontend extends CanHavePTW with TileNetwork {
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val module: HasICacheFrontendModule
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val frontend = LazyModule(new Frontend()(p.alterPartial({
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case CacheName => CacheName("L1I")
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})))
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l1backend.node := frontend.node
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nPTWPorts += 1
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}
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trait HasICacheFrontendBundle extends TileNetworkBundle {
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val outer: HasICacheFrontend
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}
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trait HasICacheFrontendModule extends CanHavePTWModule with TileNetworkModule {
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val outer: HasICacheFrontend
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//val io: HasICacheFrontendBundle
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ptwPorts += outer.frontend.module.io.ptw
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}
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@ -5,12 +5,13 @@ package rocket
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import Chisel._
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import config.{Parameters, Field}
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import coreplex._
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import diplomacy._
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import uncore.constants._
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import uncore.tilelink2._
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import uncore.util._
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import uncore.constants._
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import uncore.tilelink.{TLKey, TLId}
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import util.ParameterizedBundle
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import scala.collection.mutable.ListBuffer
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case class DCacheConfig(
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nMSHRs: Int = 1,
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@ -146,3 +147,26 @@ object HellaCache {
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else LazyModule(new NonBlockingDCache(cfg))
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}
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}
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/** Mix-ins for constructing tiles that have a HellaCache */
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trait HasHellaCache extends TileNetwork {
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val module: HasHellaCacheModule
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implicit val p: Parameters
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def findScratchpadFromICache: Option[AddressSet]
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var nDCachePorts = 0
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val dcacheParams = p.alterPartial({ case CacheName => CacheName("L1D") })
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val dcache = HellaCache(p(DCacheKey), findScratchpadFromICache _)(dcacheParams)
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l1backend.node := dcache.node
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}
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trait HasHellaCacheBundle extends TileNetworkBundle {
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val outer: HasHellaCache
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}
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trait HasHellaCacheModule extends TileNetworkModule {
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val outer: HasHellaCache
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//val io: HasHellaCacheBundle
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val dcachePorts = ListBuffer[HellaCacheIO]()
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val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.dcacheParams))
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outer.dcache.module.io.cpu <> dcacheArb.io.mem
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}
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@ -15,7 +15,7 @@ import Chisel.ImplicitConversions._
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trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
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val cacheBlockBytes = p(CacheBlockBytes)
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val lgCacheBlockBytes = log2Up(cacheBlockBytes)
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val cacheDataBits = p(TLCacheEdge).bundle.dataBits
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val cacheDataBits = p(SharedMemoryTLEdge).bundle.dataBits
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val cacheDataBeats = (cacheBlockBytes * 8) / cacheDataBits
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val refillCycles = cacheDataBeats
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}
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@ -4,11 +4,12 @@
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package rocket
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import Chisel._
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import uncore.util.PseudoLRU
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import config._
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import uncore.constants._
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import uncore.util.PseudoLRU
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import util._
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import Chisel.ImplicitConversions._
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import config._
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import scala.collection.mutable.ListBuffer
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class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
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val prv = Bits(width = 2)
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@ -217,3 +218,17 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
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}
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}
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}
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/** Mix-ins for constructing tiles that might have a PTW */
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trait CanHavePTW extends HasHellaCache {
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implicit val p: Parameters
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val module: CanHavePTWModule
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var nPTWPorts = 1
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}
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trait CanHavePTWModule extends HasHellaCacheModule {
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val outer: CanHavePTW
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val ptwPorts = ListBuffer(outer.dcache.module.io.ptw)
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val ptwOpt = if (outer.p(UseVM)) { Some(Module(new PTW(outer.nPTWPorts)(outer.p))) } else None
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ptwOpt foreach { ptw => dcachePorts += ptw.io.mem }
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}
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@ -4,16 +4,159 @@
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package rocket
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import Chisel._
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import uncore.tilelink._
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import uncore.constants._
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import uncore.util.CacheName
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import util._
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import Chisel.ImplicitConversions._
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import config._
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import coreplex._
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import diplomacy._
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import uncore.constants._
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import uncore.agents._
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import uncore.coherence._
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import uncore.devices._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.util._
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import util._
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case object RoccMaxTaggedMemXacts extends Field[Int]
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case object RoccNMemChannels extends Field[Int]
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case object RoccNPTWPorts extends Field[Int]
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case object BuildRoCC extends Field[Seq[RoccParameters]]
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trait CanHaveLegacyRoccs extends CanHaveSharedFPU with CanHavePTW with TileNetwork {
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val module: CanHaveLegacyRoccsModule
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val legacyRocc = if (p(BuildRoCC).isEmpty) None
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else Some(LazyModule(new LegacyRoccComplex()(p.alter { (site, here, up) => {
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case CacheBlockOffsetBits => log2Up(site(CacheBlockBytes))
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case AmoAluOperandBits => site(XLen)
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case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _)
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case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
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case TLId => "L1toL2"
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case TLKey("L1toL2") =>
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TileLinkParameters(
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coherencePolicy = new MESICoherence(new NullRepresentation(site(NTiles))),
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nManagers = site(BankedL2Config).nBanks + 1 /* MMIO */,
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nCachingClients = 1,
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nCachelessClients = 1,
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maxClientXacts = List(
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site(DCacheKey).nMSHRs + 1 /* IOMSHR */,
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if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)).max,
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maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
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maxManagerXacts = 8,
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dataBeats = (8 * site(CacheBlockBytes)) / site(XLen),
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dataBits = site(CacheBlockBytes)*8)
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}})))
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// TODO for now, all legacy rocc mem ports mapped to one external node
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legacyRocc foreach { lr =>
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lr.masterNodes.foreach { l1backend.node := _ }
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nPTWPorts += lr.nPTWPorts
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nDCachePorts += lr.nRocc
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}
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}
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trait CanHaveLegacyRoccsModule extends CanHaveSharedFPUModule with CanHavePTWModule with TileNetworkModule {
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val outer: CanHaveLegacyRoccs
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fpuOpt foreach { fpu =>
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outer.legacyRocc.orElse {
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fpu.io.cp_req.valid := Bool(false)
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fpu.io.cp_resp.ready := Bool(false)
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None
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} foreach { lr =>
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fpu.io.cp_req <> lr.module.io.fpu.cp_req
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fpu.io.cp_resp <> lr.module.io.fpu.cp_resp
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}
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}
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outer.legacyRocc foreach { lr =>
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ptwPorts ++= lr.module.io.ptw
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dcachePorts ++= lr.module.io.dcache
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}
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}
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class LegacyRoccComplex(implicit p: Parameters) extends LazyModule with HasCoreParameters {
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val buildRocc = p(BuildRoCC)
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val usingRocc = !buildRocc.isEmpty
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val nRocc = buildRocc.size
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val nFPUPorts = buildRocc.filter(_.useFPU).size
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val nMemChannels = buildRocc.map(_.nMemChannels).sum + nRocc
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val nPTWPorts = buildRocc.map(_.nPTWPorts).sum
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val roccOpcodes = buildRocc.map(_.opcodes)
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val legacies = List.fill(nMemChannels) { LazyModule(new TLLegacy) }
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val masterNodes = legacies.map(_ => TLOutputNode())
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legacies.zip(masterNodes).foreach { case(l,m) => m := TLHintHandler()(l.node) }
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val tl = masterNodes.map(_.bundleOut)
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val dcache = Vec(nRocc, new HellaCacheIO)
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val fpu = new Bundle {
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val cp_req = Decoupled(new FPInput())
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val cp_resp = Decoupled(new FPResult()).flip
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}
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val ptw = Vec(nPTWPorts, new TLBPTWIO)
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val core = new Bundle {
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val cmd = Decoupled(new RoCCCommand).flip
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val resp = Decoupled(new RoCCResponse)
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val busy = Bool(OUTPUT)
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val interrupt = Bool(OUTPUT)
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val exception = Bool(INPUT)
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}
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}
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val respArb = Module(new RRArbiter(new RoCCResponse, nRocc))
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io.core.resp <> respArb.io.out
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val cmdRouter = Module(new RoccCommandRouter(roccOpcodes))
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cmdRouter.io.in <> io.core.cmd
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val roccs = buildRocc.zipWithIndex.map { case (accelParams, i) =>
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val rocc = accelParams.generator(p.alterPartial({
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case RoccNMemChannels => accelParams.nMemChannels
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case RoccNPTWPorts => accelParams.nPTWPorts
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}))
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val dcIF = Module(new SimpleHellaCacheIF)
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rocc.io.cmd <> cmdRouter.io.out(i)
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rocc.io.exception := io.core.exception
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dcIF.io.requestor <> rocc.io.mem
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io.dcache(i) := dcIF.io.cache
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legacies(i).module.io.legacy <> rocc.io.autl
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respArb.io.in(i) <> Queue(rocc.io.resp)
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rocc
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}
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(nRocc to legacies.size) zip roccs.map(_.io.utl) foreach { case(i, utl) =>
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legacies(i).module.io.legacy <> utl
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}
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io.core.busy := cmdRouter.io.busy || roccs.map(_.io.busy).reduce(_ || _)
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io.core.interrupt := roccs.map(_.io.interrupt).reduce(_ || _)
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if (usingFPU && nFPUPorts > 0) {
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val fpArb = Module(new InOrderArbiter(new FPInput, new FPResult, nFPUPorts))
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val fp_rocc_ios = roccs.zip(buildRocc)
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.filter { case (_, params) => params.useFPU }
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.map { case (rocc, _) => rocc.io }
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fpArb.io.in_req <> fp_rocc_ios.map(_.fpu_req)
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fp_rocc_ios.zip(fpArb.io.in_resp).foreach {
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case (rocc, arb) => rocc.fpu_resp <> arb
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}
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io.fpu.cp_req <> fpArb.io.out_req
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fpArb.io.out_resp <> io.fpu.cp_resp
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} else {
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io.fpu.cp_req.valid := Bool(false)
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io.fpu.cp_resp.ready := Bool(false)
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}
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}
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}
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|
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case class RoccParameters(
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opcodes: OpcodeSet,
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generator: Parameters => RoCC,
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nMemChannels: Int = 0,
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nPTWPorts : Int = 0,
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useFPU: Boolean = false)
|
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|
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class RoCCInstruction extends Bundle
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{
|
||||
@ -39,26 +182,30 @@ class RoCCResponse(implicit p: Parameters) extends CoreBundle()(p) {
|
||||
val data = Bits(width = xLen)
|
||||
}
|
||||
|
||||
class RoCCInterface(implicit p: Parameters) extends CoreBundle()(p) {
|
||||
class RoCCCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
|
||||
val cmd = Decoupled(new RoCCCommand).flip
|
||||
val resp = Decoupled(new RoCCResponse)
|
||||
val mem = new HellaCacheIO
|
||||
val busy = Bool(OUTPUT)
|
||||
val interrupt = Bool(OUTPUT)
|
||||
val exception = Bool(INPUT)
|
||||
|
||||
override def cloneType = new RoCCCoreIO()(p).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
class RoCCIO(implicit p: Parameters) extends RoCCCoreIO()(p) {
|
||||
// These should be handled differently, eventually
|
||||
val autl = new ClientUncachedTileLinkIO
|
||||
val utl = Vec(p(RoccNMemChannels), new ClientUncachedTileLinkIO)
|
||||
val ptw = Vec(p(RoccNPTWPorts), new TLBPTWIO)
|
||||
val fpu_req = Decoupled(new FPInput)
|
||||
val fpu_resp = Decoupled(new FPResult).flip
|
||||
val exception = Bool(INPUT)
|
||||
|
||||
override def cloneType = new RoCCInterface().asInstanceOf[this.type]
|
||||
override def cloneType = new RoCCIO()(p).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
abstract class RoCC(implicit p: Parameters) extends CoreModule()(p) {
|
||||
val io = new RoCCInterface
|
||||
val io = new RoCCIO
|
||||
io.mem.req.bits.phys := Bool(true) // don't perform address translation
|
||||
io.mem.invalidate_lr := Bool(false) // don't mess with LR/SC
|
||||
}
|
||||
|
||||
@ -4,14 +4,13 @@
|
||||
package rocket
|
||||
|
||||
import Chisel._
|
||||
import uncore.devices._
|
||||
import uncore.util.{CacheName, CacheBlockBytes}
|
||||
import config._
|
||||
import uncore.constants._
|
||||
import uncore.tilelink2._
|
||||
import util._
|
||||
import Chisel.ImplicitConversions._
|
||||
import config._
|
||||
|
||||
case class RocketConfig(xLen: Int)
|
||||
// TODO replace some of below fields with above Config
|
||||
case object XLen extends Field[Int]
|
||||
case object FetchWidth extends Field[Int]
|
||||
case object RetireWidth extends Field[Int]
|
||||
@ -33,72 +32,6 @@ case object NBreakpoints extends Field[Int]
|
||||
case object NPerfCounters extends Field[Int]
|
||||
case object NPerfEvents extends Field[Int]
|
||||
case object DataScratchpadSize extends Field[Int]
|
||||
case object TLCacheEdge extends Field[TLEdgeOut]
|
||||
|
||||
trait HasCoreParameters {
|
||||
implicit val p: Parameters
|
||||
val xLen = p(XLen)
|
||||
val fLen = xLen // TODO relax this
|
||||
|
||||
val usingVM = p(UseVM)
|
||||
val usingUser = p(UseUser) || usingVM
|
||||
val usingDebug = p(UseDebug)
|
||||
val usingMulDiv = p(MulDivKey).nonEmpty
|
||||
val usingFPU = p(FPUKey).nonEmpty
|
||||
val usingAtomics = p(UseAtomics)
|
||||
val usingCompressed = p(UseCompressed)
|
||||
val usingRoCC = !p(BuildRoCC).isEmpty
|
||||
val fastLoadWord = p(FastLoadWord)
|
||||
val fastLoadByte = p(FastLoadByte)
|
||||
val fastJAL = p(FastJAL)
|
||||
val nBreakpoints = p(NBreakpoints)
|
||||
val nPerfCounters = p(NPerfCounters)
|
||||
val nPerfEvents = p(NPerfEvents)
|
||||
val usingDataScratchpad = p(DataScratchpadSize) > 0
|
||||
|
||||
val retireWidth = p(RetireWidth)
|
||||
val fetchWidth = p(FetchWidth)
|
||||
val coreInstBits = p(CoreInstBits)
|
||||
val coreInstBytes = coreInstBits/8
|
||||
val coreDataBits = xLen
|
||||
val coreDataBytes = coreDataBits/8
|
||||
val dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size
|
||||
val coreDCacheReqTagBits = 6
|
||||
val dcacheReqTagBits = coreDCacheReqTagBits + log2Ceil(dcacheArbPorts)
|
||||
|
||||
def pgIdxBits = 12
|
||||
def pgLevelBits = 10 - log2Ceil(xLen / 32)
|
||||
def vaddrBits = pgIdxBits + pgLevels * pgLevelBits
|
||||
val paddrBits = p(TLCacheEdge).bundle.addressBits
|
||||
def ppnBits = paddrBits - pgIdxBits
|
||||
def vpnBits = vaddrBits - pgIdxBits
|
||||
val pgLevels = p(PgLevels)
|
||||
val asIdBits = p(ASIdBits)
|
||||
val vpnBitsExtended = vpnBits + (vaddrBits < xLen).toInt
|
||||
val vaddrBitsExtended = vpnBitsExtended + pgIdxBits
|
||||
val coreMaxAddrBits = paddrBits max vaddrBitsExtended
|
||||
val nCustomMrwCsrs = p(NCustomMRWCSRs)
|
||||
|
||||
// fetchWidth doubled, but coreInstBytes halved, for RVC
|
||||
val decodeWidth = fetchWidth / (if (usingCompressed) 2 else 1)
|
||||
|
||||
// Print out log of committed instructions and their writeback values.
|
||||
// Requires post-processing due to out-of-order writebacks.
|
||||
val enableCommitLog = false
|
||||
|
||||
val maxPAddrBits = xLen match {
|
||||
case 32 => 34
|
||||
case 64 => 50
|
||||
}
|
||||
|
||||
require(paddrBits <= maxPAddrBits)
|
||||
require(!fastLoadByte || fastLoadWord)
|
||||
}
|
||||
|
||||
abstract class CoreModule(implicit val p: Parameters) extends Module
|
||||
with HasCoreParameters
|
||||
abstract class CoreBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
|
||||
with HasCoreParameters
|
||||
|
||||
class RegFile(n: Int, w: Int, zero: Boolean = false) {
|
||||
private val rf = Mem(n, UInt(width = w))
|
||||
@ -141,16 +74,7 @@ object ImmGen {
|
||||
}
|
||||
}
|
||||
|
||||
class Rocket(implicit p: Parameters) extends CoreModule()(p) {
|
||||
val io = new Bundle {
|
||||
val interrupts = new TileInterrupts().asInput
|
||||
val hartid = UInt(INPUT, xLen)
|
||||
val imem = new FrontendIO()(p.alterPartial({case CacheName => CacheName("L1I") }))
|
||||
val dmem = new HellaCacheIO()(p.alterPartial({ case CacheName => CacheName("L1D") }))
|
||||
val ptw = new DatapathPTWIO().flip
|
||||
val fpu = new FPUIO().flip
|
||||
val rocc = new RoCCInterface().flip
|
||||
}
|
||||
class Rocket(val c: RocketConfig)(implicit p: Parameters) extends CoreModule()(p) with HasCoreIO {
|
||||
|
||||
val decode_table = {
|
||||
(if (usingMulDiv) new MDecode +: (xLen > 32).option(new M64Decode).toSeq else Nil) ++:
|
||||
@ -520,7 +444,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
|
||||
csr.io.hartid := io.hartid
|
||||
io.fpu.fcsr_rm := csr.io.fcsr_rm
|
||||
csr.io.fcsr_flags := io.fpu.fcsr_flags
|
||||
csr.io.rocc.interrupt <> io.rocc.interrupt
|
||||
csr.io.rocc_interrupt := io.rocc.interrupt
|
||||
csr.io.pc := wb_reg_pc
|
||||
csr.io.badaddr := encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata)
|
||||
io.ptw.ptbr := csr.io.ptbr
|
||||
@ -101,3 +101,34 @@ class ScratchpadSlavePort(implicit p: Parameters) extends LazyModule {
|
||||
tl_in.e.ready := Bool(true)
|
||||
}
|
||||
}
|
||||
|
||||
/** Mix-ins for constructing tiles that have optional scratchpads */
|
||||
trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
|
||||
val module: CanHaveScratchpadModule
|
||||
|
||||
val slaveNode = if (p(DataScratchpadSize) == 0) None else Some(TLInputNode())
|
||||
val scratch = if (p(DataScratchpadSize) == 0) None else Some(LazyModule(new ScratchpadSlavePort()(dcacheParams)))
|
||||
|
||||
(slaveNode zip scratch) foreach { case (node, lm) => lm.node := TLFragmenter(p(XLen)/8, p(CacheBlockBytes))(node) }
|
||||
|
||||
def findScratchpadFromICache: Option[AddressSet] = scratch.map { s =>
|
||||
val finalNode = frontend.node.edgesOut(0).manager.managers.find(_.nodePath.last == s.node)
|
||||
require (finalNode.isDefined, "Could not find the scratch pad; not reachable via icache?")
|
||||
require (finalNode.get.address.size == 1, "Scratchpad address space was fragmented!")
|
||||
finalNode.get.address(0)
|
||||
}
|
||||
|
||||
nDCachePorts += 1 // core TODO dcachePorts += () => module.io.dmem ??
|
||||
}
|
||||
|
||||
trait CanHaveScratchpadBundle extends HasHellaCacheBundle with HasICacheFrontendBundle {
|
||||
val outer: CanHaveScratchpad
|
||||
val slave = outer.slaveNode.map(_.bundleIn)
|
||||
}
|
||||
|
||||
trait CanHaveScratchpadModule extends HasHellaCacheModule with HasICacheFrontendModule {
|
||||
val outer: CanHaveScratchpad
|
||||
val io: CanHaveScratchpadBundle
|
||||
|
||||
outer.scratch.foreach { lm => dcachePorts += lm.module.io.dmem }
|
||||
}
|
||||
|
||||
@ -12,6 +12,7 @@ import diplomacy._
|
||||
import uncore.util._
|
||||
import uncore.tilelink2._
|
||||
|
||||
case object PAddrBits extends Field[Int]
|
||||
case object PgLevels extends Field[Int]
|
||||
case object ASIdBits extends Field[Int]
|
||||
|
||||
|
||||
@ -4,161 +4,72 @@
|
||||
package rocket
|
||||
|
||||
import Chisel._
|
||||
import config._
|
||||
import coreplex._
|
||||
import diplomacy._
|
||||
import uncore.tilelink._
|
||||
import uncore.tilelink2._
|
||||
import uncore.util.{CacheName, CacheBlockBytes}
|
||||
import uncore.converters._
|
||||
import uncore.devices._
|
||||
import uncore.tilelink2._
|
||||
import util._
|
||||
import config._
|
||||
import scala.collection.mutable.ListBuffer
|
||||
|
||||
case object BuildRoCC extends Field[Seq[RoccParameters]]
|
||||
class RocketTile(val c: RocketConfig)(implicit p: Parameters) extends BaseTile()(p)
|
||||
with CanHaveLegacyRoccs // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache
|
||||
with CanHaveScratchpad { // implies CanHavePTW with HasHellaCache with HasICacheFrontend
|
||||
|
||||
case class RoccParameters(
|
||||
opcodes: OpcodeSet,
|
||||
generator: Parameters => RoCC,
|
||||
nMemChannels: Int = 0,
|
||||
nPTWPorts : Int = 0,
|
||||
useFPU: Boolean = false)
|
||||
nDCachePorts += 1 // core TODO dcachePorts += () => module.core.io.dmem ??
|
||||
|
||||
class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
|
||||
val coreParams = p.alterPartial {
|
||||
case TLCacheEdge => cachedOut.edgesOut(0)
|
||||
}
|
||||
val dcacheParams = coreParams.alterPartial({
|
||||
case CacheName => CacheName("L1D")
|
||||
case TLId => "L1toL2"
|
||||
})
|
||||
val icacheParams = coreParams.alterPartial({
|
||||
case CacheName => CacheName("L1I")
|
||||
case TLId => "L1toL2"
|
||||
})
|
||||
override lazy val module = new RocketTileModule(this)
|
||||
}
|
||||
|
||||
val slaveNode = if (p(DataScratchpadSize) == 0) None else Some(TLInputNode())
|
||||
val scratch = if (p(DataScratchpadSize) == 0) None else Some(LazyModule(new ScratchpadSlavePort()(dcacheParams)))
|
||||
def findScratch() = scratch.map { s =>
|
||||
val finalNode = uncachedOut.edgesOut(0).manager.managers.find(_.nodePath.last == s.node)
|
||||
require (finalNode.isDefined, "Could not find the scratch pad; not reachable via icache?")
|
||||
require (finalNode.get.address.size == 1, "Scratchpad address space was fragmented!")
|
||||
finalNode.get.address(0)
|
||||
class RocketTileBundle(outer: RocketTile) extends BaseTileBundle(outer)
|
||||
with CanHaveScratchpadBundle
|
||||
|
||||
class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => new RocketTileBundle(outer))
|
||||
with CanHaveLegacyRoccsModule
|
||||
with CanHaveScratchpadModule {
|
||||
|
||||
val core = Module(p(BuildCore)(outer.c, outer.p))
|
||||
core.io.interrupts := io.interrupts
|
||||
core.io.hartid := io.hartid
|
||||
outer.frontend.module.io.cpu <> core.io.imem
|
||||
outer.frontend.module.io.resetVector := io.resetVector
|
||||
dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ??
|
||||
fpuOpt foreach { fpu => core.io.fpu <> fpu.io }
|
||||
ptwOpt foreach { ptw => core.io.ptw <> ptw.io.dpath }
|
||||
outer.legacyRocc foreach { lr =>
|
||||
lr.module.io.core.cmd <> core.io.rocc.cmd
|
||||
lr.module.io.core.exception := core.io.rocc.exception
|
||||
core.io.rocc.resp <> lr.module.io.core.resp
|
||||
core.io.rocc.busy := lr.module.io.core.busy
|
||||
core.io.rocc.interrupt := lr.module.io.core.interrupt
|
||||
}
|
||||
|
||||
val dcache = HellaCache(p(DCacheKey), findScratch)(dcacheParams)
|
||||
val frontend = LazyModule(new Frontend()(icacheParams))
|
||||
val ucLegacy = LazyModule(new TLLegacy()(icacheParams))
|
||||
val tileXbar = LazyModule(new TLXbar)
|
||||
tileXbar.node := TLHintHandler()(ucLegacy.node)
|
||||
tileXbar.node := frontend.node
|
||||
// TODO figure out how to move the below into their respective mix-ins
|
||||
require(dcachePorts.size == core.dcacheArbPorts)
|
||||
dcacheArb.io.requestor <> dcachePorts
|
||||
ptwOpt foreach { ptw => ptw.io.requestor <> ptwPorts }
|
||||
}
|
||||
|
||||
val cachedOut = TLOutputNode()
|
||||
val uncachedOut = TLOutputNode()
|
||||
cachedOut := dcache.node
|
||||
uncachedOut := tileXbar.node
|
||||
val masterNodes = List(cachedOut, uncachedOut)
|
||||
class AsyncRocketTile(c: RocketConfig)(implicit p: Parameters) extends LazyModule {
|
||||
val rocket = LazyModule(new RocketTile(c))
|
||||
|
||||
(slaveNode zip scratch) foreach { case (node, lm) => lm.node := TLFragmenter(p(XLen)/8, p(CacheBlockBytes))(node) }
|
||||
val masterNodes = rocket.masterNodes.map(_ => TLAsyncOutputNode())
|
||||
val slaveNode = rocket.slaveNode.map(_ => TLAsyncInputNode())
|
||||
|
||||
(rocket.masterNodes zip masterNodes) foreach { case (r,n) => n := TLAsyncCrossingSource()(r) }
|
||||
(rocket.slaveNode zip slaveNode) foreach { case (r,n) => r := TLAsyncCrossingSink()(n) }
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val cached = cachedOut.bundleOut
|
||||
val uncached = uncachedOut.bundleOut
|
||||
val master = masterNodes.map(_.bundleOut)
|
||||
val slave = slaveNode.map(_.bundleIn)
|
||||
val hartid = UInt(INPUT, p(XLen))
|
||||
val interrupts = new TileInterrupts()(coreParams).asInput
|
||||
val interrupts = new TileInterrupts()(p).asInput
|
||||
val resetVector = UInt(INPUT, p(XLen))
|
||||
}
|
||||
|
||||
val buildRocc = p(BuildRoCC)
|
||||
val usingRocc = !buildRocc.isEmpty
|
||||
val nRocc = buildRocc.size
|
||||
val nFPUPorts = buildRocc.filter(_.useFPU).size
|
||||
|
||||
val core = Module(new Rocket()(dcacheParams))
|
||||
|
||||
val ptwPorts = ListBuffer(frontend.module.io.ptw, dcache.module.io.ptw)
|
||||
val dcPorts = ListBuffer(core.io.dmem)
|
||||
val uncachedArbPorts = ListBuffer[ClientUncachedTileLinkIO]()
|
||||
core.io.interrupts := io.interrupts
|
||||
core.io.hartid := io.hartid
|
||||
frontend.module.io.cpu <> core.io.imem
|
||||
frontend.module.io.resetVector := io.resetVector
|
||||
|
||||
val fpuOpt = p(FPUKey).map(cfg => Module(new FPU(cfg)(coreParams)))
|
||||
fpuOpt.foreach(fpu => core.io.fpu <> fpu.io)
|
||||
|
||||
if (usingRocc) {
|
||||
val respArb = Module(new RRArbiter(new RoCCResponse()(coreParams), nRocc))
|
||||
core.io.rocc.resp <> respArb.io.out
|
||||
|
||||
val roccOpcodes = buildRocc.map(_.opcodes)
|
||||
val cmdRouter = Module(new RoccCommandRouter(roccOpcodes)(coreParams))
|
||||
cmdRouter.io.in <> core.io.rocc.cmd
|
||||
|
||||
val roccs = buildRocc.zipWithIndex.map { case (accelParams, i) =>
|
||||
val rocc = accelParams.generator(dcacheParams.alterPartial({
|
||||
case RoccNMemChannels => accelParams.nMemChannels
|
||||
case RoccNPTWPorts => accelParams.nPTWPorts
|
||||
}))
|
||||
val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
|
||||
rocc.io.cmd <> cmdRouter.io.out(i)
|
||||
rocc.io.exception := core.io.rocc.exception
|
||||
dcIF.io.requestor <> rocc.io.mem
|
||||
dcPorts += dcIF.io.cache
|
||||
uncachedArbPorts += rocc.io.autl
|
||||
rocc
|
||||
}
|
||||
|
||||
if (nFPUPorts > 0) {
|
||||
fpuOpt.foreach { fpu =>
|
||||
val fpArb = Module(new InOrderArbiter(new FPInput()(coreParams), new FPResult()(coreParams), nFPUPorts))
|
||||
val fp_roccs = roccs.zip(buildRocc)
|
||||
.filter { case (_, params) => params.useFPU }
|
||||
.map { case (rocc, _) => rocc.io }
|
||||
fpArb.io.in_req <> fp_roccs.map(_.fpu_req)
|
||||
fp_roccs.zip(fpArb.io.in_resp).foreach {
|
||||
case (rocc, fpu_resp) => rocc.fpu_resp <> fpu_resp
|
||||
}
|
||||
fpu.io.cp_req <> fpArb.io.out_req
|
||||
fpArb.io.out_resp <> fpu.io.cp_resp
|
||||
}
|
||||
}
|
||||
|
||||
core.io.rocc.busy := cmdRouter.io.busy || roccs.map(_.io.busy).reduce(_ || _)
|
||||
core.io.rocc.interrupt := roccs.map(_.io.interrupt).reduce(_ || _)
|
||||
respArb.io.in <> roccs.map(rocc => Queue(rocc.io.resp))
|
||||
|
||||
ptwPorts ++= roccs.flatMap(_.io.ptw)
|
||||
uncachedArbPorts ++= roccs.flatMap(_.io.utl) // TODO no difference between io.autl and io.utl for now
|
||||
|
||||
val uncachedArb = Module(new ClientUncachedTileLinkIOArbiter(uncachedArbPorts.size)(icacheParams))
|
||||
uncachedArb.io.in <> uncachedArbPorts
|
||||
ucLegacy.module.io.legacy <> uncachedArb.io.out
|
||||
} else {
|
||||
ucLegacy.module.io.legacy.acquire.valid := Bool(false)
|
||||
ucLegacy.module.io.legacy.grant.ready := Bool(false)
|
||||
}
|
||||
|
||||
if (p(UseVM)) {
|
||||
val ptw = Module(new PTW(ptwPorts.size)(dcacheParams))
|
||||
ptw.io.requestor <> ptwPorts
|
||||
ptw.io.mem +=: dcPorts
|
||||
core.io.ptw <> ptw.io.dpath
|
||||
}
|
||||
|
||||
scratch.foreach { lm => lm.module.io.dmem +=: dcPorts }
|
||||
|
||||
require(dcPorts.size == core.dcacheArbPorts)
|
||||
val dcArb = Module(new HellaCacheArbiter(dcPorts.size)(dcacheParams))
|
||||
dcArb.io.requestor <> dcPorts
|
||||
dcache.module.io.cpu <> dcArb.io.mem
|
||||
|
||||
if (nFPUPorts == 0) {
|
||||
fpuOpt.foreach { fpu =>
|
||||
fpu.io.cp_req.valid := Bool(false)
|
||||
fpu.io.cp_resp.ready := Bool(false)
|
||||
}
|
||||
}
|
||||
rocket.module.io.interrupts := ShiftRegister(io.interrupts, 3)
|
||||
// signals that do not change:
|
||||
rocket.module.io.hartid := io.hartid
|
||||
rocket.module.io.resetVector := io.resetVector
|
||||
}
|
||||
}
|
||||
|
||||
@ -155,7 +155,7 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle {
|
||||
val time = UInt(OUTPUT, xLen)
|
||||
val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
|
||||
val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip
|
||||
val rocc = new RoCCInterface().flip
|
||||
val rocc_interrupt = Bool(INPUT)
|
||||
val interrupt = Bool(OUTPUT)
|
||||
val interrupt_cause = UInt(OUTPUT, xLen)
|
||||
val bp = Vec(nBreakpoints, new BP).asOutput
|
||||
@ -252,7 +252,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
|
||||
val reg_hpmcounter = reg_hpmevent.map(e => WideCounter(64, ((UInt(0) +: io.events): Seq[UInt])(e)))
|
||||
|
||||
val mip = Wire(init=reg_mip)
|
||||
mip.rocc := io.rocc.interrupt
|
||||
mip.rocc := io.rocc_interrupt
|
||||
val read_mip = mip.asUInt & supported_interrupts
|
||||
|
||||
val pending_interrupts = read_mip & reg_mie
|
||||
|
||||
Reference in New Issue
Block a user