Refactor Tile to use cake pattern (#502)
* [rocket] Refactor Tile into cake pattern with traits * [rocket] cacheDataBits &etc in HasCoreParameters * [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters * [rocket] frontend and icache now diplomatic * [rocket] file name capitalization * [rocket] re-add hook for inserting externally-defined Cores * [rocket] add FPUCoreIO * [groundtest] move TL1 Config instances to where they are used * [unittest] remove legacy unit tests * [groundtest] remove legacy device tests
This commit is contained in:
Henry Cook
GitHub
@ -4,16 +4,10 @@ package coreplex
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import Chisel._
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import config._
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import junctions._
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import diplomacy._
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import uncore.tilelink._
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import rocket.{TileInterrupts, XLen}
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import uncore.tilelink2._
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import uncore.coherence._
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import uncore.agents._
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import uncore.devices._
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import uncore.util._
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import uncore.converters._
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import rocket._
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import util._
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/** Widths of various points in the SoC */
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@ -56,102 +50,17 @@ trait HasCoreplexParameters {
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case class CoreplexParameters(implicit val p: Parameters) extends HasCoreplexParameters
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abstract class BareCoreplex(implicit p: Parameters) extends LazyModule
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abstract class BareCoreplexBundle[+L <: BareCoreplex](_outer: L) extends GenericParameterizedBundle(_outer) {
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val outer = _outer
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implicit val p = outer.p
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}
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abstract class BareCoreplexModule[+L <: BareCoreplex, +B <: BareCoreplexBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
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val outer = _outer
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val io = _io ()
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}
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trait CoreplexNetwork extends HasCoreplexParameters {
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val module: CoreplexNetworkModule
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val l1tol2 = LazyModule(new TLXbar)
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val l1tol2_beatBytes = l1tol2Config.beatBytes
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val l1tol2_lineBytes = p(CacheBlockBytes)
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val cbus = LazyModule(new TLXbar)
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val cbus_beatBytes = cbusConfig.beatBytes
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val cbus_lineBytes = l1tol2_lineBytes
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val intBar = LazyModule(new IntXbar)
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val mmio = TLOutputNode()
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val mmioInt = IntInputNode()
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intBar.intnode := mmioInt
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cbus.node :=
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TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata
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TLWidthWidget(l1tol2_beatBytes)(
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TLBuffer()(
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l1tol2.node)))
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mmio :=
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TLBuffer()(
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TLWidthWidget(l1tol2_beatBytes)(
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l1tol2.node))
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}
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trait CoreplexNetworkBundle extends HasCoreplexParameters {
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val outer: CoreplexNetwork
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val mmio = outer.mmio.bundleOut
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val interrupts = outer.mmioInt.bundleIn
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}
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trait CoreplexNetworkModule extends HasCoreplexParameters {
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val outer: CoreplexNetwork
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val io: CoreplexNetworkBundle
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println("\nGenerated Address Map")
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for (manager <- outer.l1tol2.node.edgesIn(0).manager.managers) {
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val prot = (if (manager.supportsGet) "R" else "") +
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(if (manager.supportsPutFull) "W" else "") +
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(if (manager.executable) "X" else "") +
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(if (manager.supportsAcquire) " [C]" else "")
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manager.address.foreach { a =>
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println(f"\t${manager.name}%s ${a.base}%x - ${a.base+a.mask+1}%x, $prot")
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}
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}
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}
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trait BankedL2CoherenceManagers extends CoreplexNetwork {
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val module: BankedL2CoherenceManagersModule
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require (isPow2(l2Config.nBanksPerChannel))
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require (isPow2(l1tol2_lineBytes))
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val mem = Seq.fill(l2Config.nMemoryChannels) {
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val bankBar = LazyModule(new TLXbar)
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val output = TLOutputNode()
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output := bankBar.node
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val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes)
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for (i <- 0 until l2Config.nBanksPerChannel) {
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val (in, out) = l2Config.coherenceManager(p)
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in := TLFilter(AddressSet(i * l1tol2_lineBytes, mask))(l1tol2.node)
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bankBar.node := out
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}
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output
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}
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}
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trait BankedL2CoherenceManagersBundle extends CoreplexNetworkBundle {
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val outer: BankedL2CoherenceManagers
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require (l2Config.nMemoryChannels <= 1, "Seq in Chisel Bundle needed to support > 1") // !!!
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val mem = outer.mem.map(_.bundleOut).toList.headOption // .headOption should be removed !!!
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}
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trait BankedL2CoherenceManagersModule extends CoreplexNetworkModule {
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val outer: BankedL2CoherenceManagers
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val io: BankedL2CoherenceManagersBundle
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}
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abstract class BaseCoreplex(implicit p: Parameters) extends BareCoreplex
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with CoreplexNetwork
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with BankedL2CoherenceManagers {
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56
src/main/scala/coreplex/BaseTile.scala
Normal file
56
src/main/scala/coreplex/BaseTile.scala
Normal file
@ -0,0 +1,56 @@
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// See LICENSE.SiFive for license details.
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package coreplex
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import Chisel._
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import config._
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import diplomacy._
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import rocket.{TileInterrupts, XLen}
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import uncore.tilelink2._
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import util.GenericParameterizedBundle
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abstract class BareTile(implicit p: Parameters) extends LazyModule
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abstract class BareTileBundle[+L <: BareTile](_outer: L) extends GenericParameterizedBundle(_outer) {
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val outer = _outer
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implicit val p = outer.p
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}
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abstract class BareTileModule[+L <: BareTile, +B <: BareTileBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
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val outer = _outer
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val io = _io ()
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}
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// Uses a tile-internal crossbar to provide a single TileLink master port
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trait TileNetwork {
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implicit val p: Parameters
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val module: TileNetworkModule
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val l1backend = LazyModule(new TLXbar)
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val masterNodes = List(TLOutputNode())
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masterNodes.head := l1backend.node
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}
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trait TileNetworkBundle {
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val outer: TileNetwork
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val master = outer.masterNodes.head.bundleOut
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}
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trait TileNetworkModule {
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val outer: TileNetwork
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val io: TileNetworkBundle
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}
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abstract class BaseTile(implicit p: Parameters) extends BareTile
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with TileNetwork {
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override lazy val module = new BaseTileModule(this, () => new BaseTileBundle(this))
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}
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class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
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with TileNetworkBundle {
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val hartid = UInt(INPUT, p(XLen))
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val interrupts = new TileInterrupts()(p).asInput
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val resetVector = UInt(INPUT, p(XLen))
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}
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class BaseTileModule[+L <: BaseTile, +B <: BaseTileBundle[L]](_outer: L, _io: () => B) extends BareTileModule(_outer, _io)
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with TileNetworkModule
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@ -6,14 +6,10 @@ package coreplex
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import Chisel._
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import config._
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import diplomacy._
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import junctions.PAddrBits
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import rocket._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.coherence._
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import uncore.agents._
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import uncore.devices._
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import uncore.converters._
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import uncore.devices._
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import uncore.tilelink2._
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import uncore.util._
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import util._
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@ -44,15 +40,8 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
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//L1DataCache
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case DCacheKey => DCacheConfig(nMSHRs = 2)
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case DataScratchpadSize => 0
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//L2 Memory System Params
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case AmoAluOperandBits => site(XLen)
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case NAcquireTransactors => 7
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case L2StoreDataQueueDepth => 1
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case L2DirectoryRepresentation => new NullRepresentation(site(NTiles))
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//Tile Constants
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case BuildRoCC => Nil
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case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _)
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case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
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//Rocket Core Constants
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case CoreInstBits => if (site(UseCompressed)) 16 else 32
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case FetchWidth => if (site(UseCompressed)) 2 else 1
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@ -76,37 +65,15 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
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case MtvecInit => Some(BigInt(0))
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case MtvecWritable => true
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//Uncore Paramters
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case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
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case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
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log2Up(site(TLKey(site(TLId))).nClients)
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case CBusConfig => TLBusConfig(beatBytes = site(XLen)/8)
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case L1toL2Config => TLBusConfig(beatBytes = site(XLen)/8) // increase for more PCIe bandwidth
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case TLKey("L1toL2") => {
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val useMEI = site(NTiles) <= 1
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TileLinkParameters(
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coherencePolicy = (
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if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
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else new MESICoherence(site(L2DirectoryRepresentation))),
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nManagers = site(BankedL2Config).nBanks + 1 /* MMIO */,
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nCachingClients = 1,
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nCachelessClients = 1,
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maxClientXacts = List(
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// L1 cache
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site(DCacheKey).nMSHRs + 1 /* IOMSHR */,
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// RoCC
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if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)).max,
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maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
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maxManagerXacts = site(NAcquireTransactors) + 2,
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dataBeats = (8 * site(CacheBlockBytes)) / site(XLen),
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dataBits = site(CacheBlockBytes)*8)
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}
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case BootROMFile => "./bootrom/bootrom.img"
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case NTiles => 1
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case NTiles => site(RocketConfigs).size
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case RocketConfigs => List(RocketConfig(site(XLen)))
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case BuildCore => (c: RocketConfig, p: Parameters) => new Rocket(c)(p)
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case BroadcastConfig => BroadcastConfig()
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case BankedL2Config => BankedL2Config()
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case CacheBlockBytes => 64
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case CacheBlockOffsetBits => log2Up(site(CacheBlockBytes))
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case EnableL2Logging => false
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})
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class WithNCores(n: Int) extends Config((site, here, up) => {
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@ -185,7 +152,7 @@ class WithStatelessBridge extends Config((site, here, up) => {
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case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
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})
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class WithL2Capacity(size_kb: Int) extends Config(Parameters.empty)
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class WithL2Capacity(size_kb: Int) extends Config(Parameters.empty) // TODO
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class WithNL2Ways(n: Int) extends Config((site, here, up) => {
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case CacheName("L2") => up(CacheName("L2"), site).copy(nWays = n)
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@ -205,7 +172,6 @@ class WithSmallCores extends Config((site, here, up) => {
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case FPUKey => None
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case UseVM => false
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case BtbKey => BtbParameters(nEntries = 0)
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case NAcquireTransactors => 2
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case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = 64, nWays = 1, nTLBEntries = 4)
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case CacheName("L1I") => up(CacheName("L1I"), site).copy(nSets = 64, nWays = 1, nTLBEntries = 4)
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case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
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@ -4,69 +4,43 @@ package coreplex
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import Chisel._
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import config._
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import junctions._
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import diplomacy._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.util._
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import util._
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import rocket._
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/////
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trait L2MasterPort extends CoreplexNetwork
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{
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val module: L2MasterPortModule
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val l2in = TLInputNode()
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l1tol2.node := l2in
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}
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trait L2MasterPortBundle extends CoreplexNetworkBundle
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{
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val outer: L2MasterPort
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val l2in = outer.l2in.bundleIn
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}
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trait L2MasterPortModule extends CoreplexNetworkModule
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{
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val outer: L2MasterPort
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val io: L2MasterPortBundle
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}
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/////
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class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex
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with CoreplexRISCVPlatform
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with L2MasterPort
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with RocketTiles {
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with HasL2MasterPort
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with HasSynchronousRocketTiles {
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override lazy val module = new DefaultCoreplexModule(this, () => new DefaultCoreplexBundle(this))
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}
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class DefaultCoreplexBundle[+L <: DefaultCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
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with CoreplexRISCVPlatformBundle
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with L2MasterPortBundle
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with RocketTilesBundle
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with HasL2MasterPortBundle
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with HasSynchronousRocketTilesBundle
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class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
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with CoreplexRISCVPlatformModule
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with L2MasterPortModule
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with RocketTilesModule
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with HasL2MasterPortModule
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with HasSynchronousRocketTilesModule
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/////
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class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex
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with CoreplexRISCVPlatform
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with L2MasterPort
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with AsyncRocketTiles {
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with HasL2MasterPort
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with HasAsynchronousRocketTiles {
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override lazy val module = new MultiClockCoreplexModule(this, () => new MultiClockCoreplexBundle(this))
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}
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class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
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with CoreplexRISCVPlatformBundle
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with L2MasterPortBundle
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with AsyncRocketTilesBundle
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with HasL2MasterPortBundle
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with HasAsynchronousRocketTilesBundle
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class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
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with CoreplexRISCVPlatformModule
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with L2MasterPortModule
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with AsyncRocketTilesModule
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with HasL2MasterPortModule
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with HasAsynchronousRocketTilesModule
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117
src/main/scala/coreplex/CoreplexNetwork.scala
Normal file
117
src/main/scala/coreplex/CoreplexNetwork.scala
Normal file
@ -0,0 +1,117 @@
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// See LICENSE.SiFive for license details.
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package coreplex
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import Chisel._
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import config._
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import diplomacy._
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import uncore.tilelink2._
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import uncore.util._
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import util._
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trait CoreplexNetwork extends HasCoreplexParameters {
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val module: CoreplexNetworkModule
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val l1tol2 = LazyModule(new TLXbar)
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val l1tol2_beatBytes = l1tol2Config.beatBytes
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val l1tol2_lineBytes = p(CacheBlockBytes)
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val cbus = LazyModule(new TLXbar)
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val cbus_beatBytes = cbusConfig.beatBytes
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val cbus_lineBytes = l1tol2_lineBytes
|
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val intBar = LazyModule(new IntXbar)
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val mmio = TLOutputNode()
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val mmioInt = IntInputNode()
|
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intBar.intnode := mmioInt
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cbus.node :=
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TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata
|
||||
TLWidthWidget(l1tol2_beatBytes)(
|
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TLBuffer()(
|
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l1tol2.node)))
|
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|
||||
mmio :=
|
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TLBuffer()(
|
||||
TLWidthWidget(l1tol2_beatBytes)(
|
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l1tol2.node))
|
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}
|
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|
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trait CoreplexNetworkBundle extends HasCoreplexParameters {
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val outer: CoreplexNetwork
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val mmio = outer.mmio.bundleOut
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val interrupts = outer.mmioInt.bundleIn
|
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}
|
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|
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trait CoreplexNetworkModule extends HasCoreplexParameters {
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val outer: CoreplexNetwork
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val io: CoreplexNetworkBundle
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|
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println("\nGenerated Address Map")
|
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for (manager <- outer.l1tol2.node.edgesIn(0).manager.managers) {
|
||||
val prot = (if (manager.supportsGet) "R" else "") +
|
||||
(if (manager.supportsPutFull) "W" else "") +
|
||||
(if (manager.executable) "X" else "") +
|
||||
(if (manager.supportsAcquire) " [C]" else "")
|
||||
manager.address.foreach { a =>
|
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println(f"\t${manager.name}%s ${a.base}%x - ${a.base+a.mask+1}%x, $prot")
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/////
|
||||
|
||||
trait BankedL2CoherenceManagers extends CoreplexNetwork {
|
||||
val module: BankedL2CoherenceManagersModule
|
||||
|
||||
require (isPow2(l2Config.nBanksPerChannel))
|
||||
require (isPow2(l1tol2_lineBytes))
|
||||
|
||||
val mem = Seq.fill(l2Config.nMemoryChannels) {
|
||||
val bankBar = LazyModule(new TLXbar)
|
||||
val output = TLOutputNode()
|
||||
|
||||
output := bankBar.node
|
||||
val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes)
|
||||
for (i <- 0 until l2Config.nBanksPerChannel) {
|
||||
val (in, out) = l2Config.coherenceManager(p)
|
||||
in := TLFilter(AddressSet(i * l1tol2_lineBytes, mask))(l1tol2.node)
|
||||
bankBar.node := out
|
||||
}
|
||||
|
||||
output
|
||||
}
|
||||
}
|
||||
|
||||
trait BankedL2CoherenceManagersBundle extends CoreplexNetworkBundle {
|
||||
val outer: BankedL2CoherenceManagers
|
||||
|
||||
require (l2Config.nMemoryChannels <= 1, "Seq in Chisel Bundle needed to support > 1") // !!!
|
||||
val mem = outer.mem.map(_.bundleOut).toList.headOption // .headOption should be removed !!!
|
||||
}
|
||||
|
||||
trait BankedL2CoherenceManagersModule extends CoreplexNetworkModule {
|
||||
val outer: BankedL2CoherenceManagers
|
||||
val io: BankedL2CoherenceManagersBundle
|
||||
}
|
||||
|
||||
/////
|
||||
|
||||
trait HasL2MasterPort extends CoreplexNetwork {
|
||||
val module: HasL2MasterPortModule
|
||||
val l2in = TLInputNode()
|
||||
l1tol2.node := l2in
|
||||
}
|
||||
|
||||
trait HasL2MasterPortBundle extends CoreplexNetworkBundle {
|
||||
val outer: HasL2MasterPort
|
||||
val l2in = outer.l2in.bundleIn
|
||||
}
|
||||
|
||||
trait HasL2MasterPortModule extends CoreplexNetworkModule {
|
||||
val outer: HasL2MasterPort
|
||||
val io: HasL2MasterPortBundle
|
||||
}
|
||||
@ -5,86 +5,67 @@ package coreplex
|
||||
import Chisel._
|
||||
import config._
|
||||
import diplomacy._
|
||||
import uncore.tilelink2._
|
||||
import uncore.coherence._
|
||||
import rocket._
|
||||
import uncore.devices.NTiles
|
||||
import uncore.tilelink2._
|
||||
|
||||
trait RocketTiles extends CoreplexRISCVPlatform {
|
||||
val module: RocketTilesModule
|
||||
case object RocketConfigs extends Field[Seq[RocketConfig]]
|
||||
|
||||
val rocketTiles = List.tabulate(p(NTiles)) { i => LazyModule(new RocketTile(i)) }
|
||||
val tileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() }
|
||||
trait HasSynchronousRocketTiles extends CoreplexRISCVPlatform {
|
||||
val module: HasSynchronousRocketTilesModule
|
||||
|
||||
val rocketTiles: Seq[RocketTile] = p(RocketConfigs).map { c =>
|
||||
LazyModule(new RocketTile(c)(p.alterPartial {
|
||||
case SharedMemoryTLEdge => l1tol2.node.edgesIn(0)
|
||||
case PAddrBits => l1tol2.node.edgesIn(0).bundle.addressBits
|
||||
}))}
|
||||
|
||||
tileIntNodes.foreach { _ := plic.intnode }
|
||||
rocketTiles.foreach { r =>
|
||||
r.masterNodes.foreach { l1tol2.node := _ }
|
||||
r.slaveNode.foreach { _ := cbus.node }
|
||||
l1tol2.node := r.cachedOut
|
||||
l1tol2.node := r.uncachedOut
|
||||
}
|
||||
|
||||
val rocketTileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() }
|
||||
rocketTileIntNodes.foreach { _ := plic.intnode }
|
||||
}
|
||||
|
||||
trait RocketTilesBundle extends CoreplexRISCVPlatformBundle {
|
||||
val outer: RocketTiles
|
||||
trait HasSynchronousRocketTilesBundle extends CoreplexRISCVPlatformBundle {
|
||||
val outer: HasSynchronousRocketTiles
|
||||
}
|
||||
|
||||
trait RocketTilesModule extends CoreplexRISCVPlatformModule {
|
||||
val outer: RocketTiles
|
||||
val io: RocketTilesBundle
|
||||
trait HasSynchronousRocketTilesModule extends CoreplexRISCVPlatformModule {
|
||||
val outer: HasSynchronousRocketTiles
|
||||
val io: HasSynchronousRocketTilesBundle
|
||||
|
||||
outer.rocketTiles.map(_.module).zipWithIndex.foreach { case (tile, i) =>
|
||||
tile.io.hartid := UInt(i)
|
||||
tile.io.resetVector := io.resetVector
|
||||
tile.io.interrupts := outer.clint.module.io.tiles(i)
|
||||
tile.io.interrupts.debug := outer.debug.module.io.debugInterrupts(i)
|
||||
tile.io.interrupts.meip := outer.tileIntNodes(i).bundleOut(0)(0)
|
||||
tile.io.interrupts.seip.foreach(_ := outer.tileIntNodes(i).bundleOut(0)(1))
|
||||
tile.io.interrupts.meip := outer.rocketTileIntNodes(i).bundleOut(0)(0)
|
||||
tile.io.interrupts.seip.foreach(_ := outer.rocketTileIntNodes(i).bundleOut(0)(1))
|
||||
}
|
||||
}
|
||||
|
||||
class AsyncRocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
|
||||
val rocket = LazyModule(new RocketTile(tileId))
|
||||
trait HasAsynchronousRocketTiles extends CoreplexRISCVPlatform {
|
||||
val module: HasAsynchronousRocketTilesModule
|
||||
|
||||
val cachedOut = TLAsyncOutputNode()
|
||||
val uncachedOut = TLAsyncOutputNode()
|
||||
val slaveNode = rocket.slaveNode.map(_ => TLAsyncInputNode())
|
||||
val rocketTiles: Seq[AsyncRocketTile] = p(RocketConfigs).map { c =>
|
||||
LazyModule(new AsyncRocketTile(c)(p.alterPartial {
|
||||
case SharedMemoryTLEdge => l1tol2.node.edgesIn(0)
|
||||
case PAddrBits => l1tol2.node.edgesIn(0).bundle.addressBits
|
||||
}))}
|
||||
|
||||
cachedOut := TLAsyncCrossingSource()(rocket.cachedOut)
|
||||
uncachedOut := TLAsyncCrossingSource()(rocket.uncachedOut)
|
||||
(rocket.slaveNode zip slaveNode) foreach { case (r,n) => r := TLAsyncCrossingSink()(n) }
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val cached = cachedOut.bundleOut
|
||||
val uncached = uncachedOut.bundleOut
|
||||
val slave = slaveNode.map(_.bundleIn)
|
||||
val hartid = UInt(INPUT, p(XLen))
|
||||
val interrupts = new TileInterrupts()(rocket.coreParams).asInput
|
||||
val resetVector = UInt(INPUT, p(XLen))
|
||||
}
|
||||
rocket.module.io.interrupts := ShiftRegister(io.interrupts, 3)
|
||||
// signals that do not change:
|
||||
rocket.module.io.hartid := io.hartid
|
||||
rocket.module.io.resetVector := io.resetVector
|
||||
}
|
||||
}
|
||||
|
||||
trait AsyncRocketTiles extends CoreplexRISCVPlatform {
|
||||
val module: AsyncRocketTilesModule
|
||||
|
||||
val rocketTiles = List.tabulate(p(NTiles)) { i => LazyModule(new AsyncRocketTile(i)) }
|
||||
val tileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() }
|
||||
|
||||
tileIntNodes.foreach { _ := plic.intnode }
|
||||
rocketTiles.foreach { r =>
|
||||
r.masterNodes.foreach { l1tol2.node := TLAsyncCrossingSink()(_) }
|
||||
r.slaveNode.foreach { _ := TLAsyncCrossingSource()(cbus.node) }
|
||||
l1tol2.node := TLAsyncCrossingSink()(r.cachedOut)
|
||||
l1tol2.node := TLAsyncCrossingSink()(r.uncachedOut)
|
||||
}
|
||||
|
||||
val rocketTileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() }
|
||||
rocketTileIntNodes.foreach { _ := plic.intnode }
|
||||
}
|
||||
|
||||
trait AsyncRocketTilesBundle extends CoreplexRISCVPlatformBundle {
|
||||
val outer: AsyncRocketTiles
|
||||
trait HasAsynchronousRocketTilesBundle extends CoreplexRISCVPlatformBundle {
|
||||
val outer: HasAsynchronousRocketTiles
|
||||
|
||||
val tcrs = Vec(nTiles, new Bundle {
|
||||
val clock = Clock(INPUT)
|
||||
@ -92,9 +73,9 @@ trait AsyncRocketTilesBundle extends CoreplexRISCVPlatformBundle {
|
||||
})
|
||||
}
|
||||
|
||||
trait AsyncRocketTilesModule extends CoreplexRISCVPlatformModule {
|
||||
val outer: AsyncRocketTiles
|
||||
val io: AsyncRocketTilesBundle
|
||||
trait HasAsynchronousRocketTilesModule extends CoreplexRISCVPlatformModule {
|
||||
val outer: HasAsynchronousRocketTiles
|
||||
val io: HasAsynchronousRocketTilesBundle
|
||||
|
||||
outer.rocketTiles.map(_.module).zipWithIndex.foreach { case (tile, i) =>
|
||||
tile.clock := io.tcrs(i).clock
|
||||
@ -103,7 +84,7 @@ trait AsyncRocketTilesModule extends CoreplexRISCVPlatformModule {
|
||||
tile.io.resetVector := io.resetVector
|
||||
tile.io.interrupts := outer.clint.module.io.tiles(i)
|
||||
tile.io.interrupts.debug := outer.debug.module.io.debugInterrupts(i)
|
||||
tile.io.interrupts.meip := outer.tileIntNodes(i).bundleOut(0)(0)
|
||||
tile.io.interrupts.seip.foreach(_ := outer.tileIntNodes(i).bundleOut(0)(1))
|
||||
tile.io.interrupts.meip := outer.rocketTileIntNodes(i).bundleOut(0)(0)
|
||||
tile.io.interrupts.seip.foreach(_ := outer.rocketTileIntNodes(i).bundleOut(0)(1))
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user