diff --git a/src/main/scala/unittest/Configs.scala b/src/main/scala/unittest/Configs.scala
index 9d71e078..3f0d2f8a 100644
--- a/src/main/scala/unittest/Configs.scala
+++ b/src/main/scala/unittest/Configs.scala
@@ -19,15 +19,15 @@ class WithUncoreUnitTests extends Config((site, here, up) => {
     val txns = 100 * site(TestDurationMultiplier)
     val timeout = 50000 * site(TestDurationMultiplier)
     Seq(
-      Module(new uncore.tilelink2.TLFuzzRAMTest(  txns=5*txns, timeout=timeout)),
-      Module(new uncore.ahb.AHBBridgeTest(true,   txns=5*txns, timeout=timeout)),
-      Module(new uncore.ahb.AHBNativeTest(true,   txns=5*txns, timeout=timeout)),
-      Module(new uncore.ahb.AHBNativeTest(false,  txns=5*txns, timeout=timeout)),
-      Module(new uncore.apb.APBBridgeTest(true,   txns=5*txns, timeout=timeout)),
-      Module(new uncore.apb.APBBridgeTest(false,  txns=5*txns, timeout=timeout)),
-      Module(new uncore.axi4.AXI4LiteFuzzRAMTest( txns=5*txns, timeout=timeout)),
-      Module(new uncore.axi4.AXI4FullFuzzRAMTest( txns=5*txns, timeout=timeout)),
-      Module(new uncore.axi4.AXI4BridgeTest(      txns=5*txns, timeout=timeout))) }
+      Module(new uncore.tilelink2.TLFuzzRAMTest(  txns=3*txns, timeout=timeout)),
+      Module(new uncore.ahb.AHBBridgeTest(true,   txns=8*txns, timeout=timeout)),
+      Module(new uncore.ahb.AHBNativeTest(true,   txns=6*txns, timeout=timeout)),
+      Module(new uncore.ahb.AHBNativeTest(false,  txns=6*txns, timeout=timeout)),
+      Module(new uncore.apb.APBBridgeTest(true,   txns=6*txns, timeout=timeout)),
+      Module(new uncore.apb.APBBridgeTest(false,  txns=6*txns, timeout=timeout)),
+      Module(new uncore.axi4.AXI4LiteFuzzRAMTest( txns=6*txns, timeout=timeout)),
+      Module(new uncore.axi4.AXI4FullFuzzRAMTest( txns=3*txns, timeout=timeout)),
+      Module(new uncore.axi4.AXI4BridgeTest(      txns=3*txns, timeout=timeout))) }
 })
 
 class WithTLSimpleUnitTests extends Config((site, here, up) => {
@@ -36,15 +36,15 @@ class WithTLSimpleUnitTests extends Config((site, here, up) => {
     val txns = 100 * site(TestDurationMultiplier)
     val timeout = 50000 * site(TestDurationMultiplier)
     Seq(
-      Module(new uncore.tilelink2.TLRAMSimpleTest(1,        txns=5*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMSimpleTest(4,        txns=5*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMSimpleTest(16,       txns=5*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMZeroDelayTest(4,     txns=5*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRR0Test(                txns=5*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRR1Test(                txns=5*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMRationalCrossingTest(txns=5*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMAsyncCrossingTest(   txns=5*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMAtomicAutomataTest(  txns=5*txns, timeout=timeout)) ) }
+      Module(new uncore.tilelink2.TLRAMSimpleTest(1,        txns=15*txns, timeout=timeout)),
+      Module(new uncore.tilelink2.TLRAMSimpleTest(4,        txns=15*txns, timeout=timeout)),
+      Module(new uncore.tilelink2.TLRAMSimpleTest(16,       txns=15*txns, timeout=timeout)),
+      Module(new uncore.tilelink2.TLRAMZeroDelayTest(4,     txns=15*txns, timeout=timeout)),
+      Module(new uncore.tilelink2.TLRR0Test(                txns= 3*txns, timeout=timeout)),
+      Module(new uncore.tilelink2.TLRR1Test(                txns= 3*txns, timeout=timeout)),
+      Module(new uncore.tilelink2.TLRAMRationalCrossingTest(txns= 3*txns, timeout=timeout)),
+      Module(new uncore.tilelink2.TLRAMAsyncCrossingTest(   txns= 5*txns, timeout=timeout)),
+      Module(new uncore.tilelink2.TLRAMAtomicAutomataTest(  txns=10*txns, timeout=timeout)) ) }
 })
 
 class WithTLWidthUnitTests extends Config((site, here, up) => {
@@ -53,12 +53,12 @@ class WithTLWidthUnitTests extends Config((site, here, up) => {
     val txns = 100 * site(TestDurationMultiplier)
     val timeout = 50000 * site(TestDurationMultiplier)
     Seq(
-      Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 256, txns=5*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMFragmenterTest(16,  64, txns=5*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMFragmenterTest( 4,  16, txns=5*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 1,  1, txns=5*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 4, 64, txns=5*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLRAMWidthWidgetTest(64,  4, txns=5*txns, timeout=timeout)) ) }
+      Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 256, txns= 5*txns, timeout=timeout)),
+      Module(new uncore.tilelink2.TLRAMFragmenterTest(16,  64, txns=15*txns, timeout=timeout)),
+      Module(new uncore.tilelink2.TLRAMFragmenterTest( 4,  16, txns=15*txns, timeout=timeout)),
+      Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 1,  1, txns= 1*txns, timeout=timeout)),
+      Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 4, 64, txns= 4*txns, timeout=timeout)),
+      Module(new uncore.tilelink2.TLRAMWidthWidgetTest(64,  4, txns= 5*txns, timeout=timeout)) ) }
 })
 
 class WithTLXbarUnitTests extends Config((site, here, up) => {
@@ -70,7 +70,7 @@ class WithTLXbarUnitTests extends Config((site, here, up) => {
       Module(new uncore.tilelink2.TLRAMXbarTest(1,           txns=5*txns, timeout=timeout)),
       Module(new uncore.tilelink2.TLRAMXbarTest(2,           txns=5*txns, timeout=timeout)),
       Module(new uncore.tilelink2.TLRAMXbarTest(8,           txns=5*txns, timeout=timeout)),
-      Module(new uncore.tilelink2.TLMulticlientXbarTest(4,4, txns=5*txns, timeout=timeout)) ) }
+      Module(new uncore.tilelink2.TLMulticlientXbarTest(4,4, txns=2*txns, timeout=timeout)) ) }
 })
 
 class UncoreUnitTestConfig extends Config(new WithUncoreUnitTests ++ new WithTestDuration(10) ++ new BasePlatformConfig)