riscv/rocket-chip
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generalize interface to DecodeLogic

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This commit is contained in:
Andrew Waterman 2012-08-22 13:38:07 -07:00
parent 0f20771664
commit 743e032f06
2 changed files with 7 additions and 7 deletions
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4
rocket/src/main/scala/consts.scala
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@ -57,8 +57,8 @@ object Constants
val DIV_RU = UFix(3, 2); val DIV_RU = UFix(3, 2);
val X = Bits("b?", 1) val X = Bits("b?", 1)
val N = UFix(0, 1); val N = Bits(0, 1);
val Y = UFix(1, 1); val Y = Bits(1, 1);
val WA_X = X val WA_X = X
val WA_RD = N val WA_RD = N

10
rocket/src/main/scala/decode.scala
View File

@ -13,32 +13,32 @@ object DecodeLogic
new Term(b.value) new Term(b.value)
} }
} }
def logic(addr: Bits, keys: Seq[Bits], cache: scala.collection.mutable.Map[Term,Bits], terms: Set[Term]) = { def logic(addr: Bits, cache: scala.collection.mutable.Map[Term,Bits], terms: Set[Term]) = {
terms.map { t => terms.map { t =>
if (!cache.contains(t)) if (!cache.contains(t))
cache += t -> ((if (t.mask == 0) addr else addr & Lit(BigInt(2).pow(addr.width)-(t.mask+1), addr.width){Bits()}) === Lit(t.value, addr.width){Bits()}) cache += t -> ((if (t.mask == 0) addr else addr & Lit(BigInt(2).pow(addr.width)-(t.mask+1), addr.width){Bits()}) === Lit(t.value, addr.width){Bits()})
cache(t) cache(t)
}.foldLeft(Bool(false))(_||_) }.foldLeft(Bool(false))(_||_)
} }
def apply(addr: Bits, default: List[Bits], mapping: Array[(Bits, List[Bits])]) = { def apply(addr: Bits, default: Iterable[Bits], mapping: Iterable[(Bits, Iterable[Bits])]) = {
var map = mapping var map = mapping
var cache = scala.collection.mutable.Map[Term,Bits]() var cache = scala.collection.mutable.Map[Term,Bits]()
default map { d => default map { d =>
val dlit = d.litOf val dlit = d.litOf
val dterm = term(dlit) val dterm = term(dlit)
val (keys, values) = map.unzip val (keys, values) = map.unzip
val keysterms = keys.map(k => term(k.litOf)) zip values.map(v => term(v.head.litOf)) val keysterms = keys.toList.map(k => term(k.litOf)) zip values.toList.map(v => term(v.head.litOf))
val result = (0 until math.max(dlit.width, values.map(_.head.litOf.width).max)).map({ case (i: Int) => val result = (0 until math.max(dlit.width, values.map(_.head.litOf.width).max)).map({ case (i: Int) =>
if (((dterm.mask >> i) & 1) != 0) { if (((dterm.mask >> i) & 1) != 0) {
var mint = keysterms.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == 1 }.map(_._1).toSet var mint = keysterms.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == 1 }.map(_._1).toSet
var maxt = keysterms.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == 0 }.map(_._1).toSet var maxt = keysterms.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == 0 }.map(_._1).toSet
logic(addr, keys, cache, SimplifyDC(mint, maxt, addr.width)).toBits logic(addr, cache, SimplifyDC(mint, maxt, addr.width)).toBits
} else { } else {
val want = 1 - ((dterm.value.toInt >> i) & 1) val want = 1 - ((dterm.value.toInt >> i) & 1)
val mint = keysterms.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == want }.map(_._1).toSet val mint = keysterms.filter { case (k,t) => ((t.mask >> i) & 1) == 0 && ((t.value >> i) & 1) == want }.map(_._1).toSet
val dc = keysterms.filter { case (k,t) => ((t.mask >> i) & 1) == 1 }.map(_._1).toSet val dc = keysterms.filter { case (k,t) => ((t.mask >> i) & 1) == 1 }.map(_._1).toSet
val bit = logic(addr, keys, cache, Simplify(mint, dc, addr.width)).toBits val bit = logic(addr, cache, Simplify(mint, dc, addr.width)).toBits
if (want == 1) bit else ~bit if (want == 1) bit else ~bit
} }
}).reverse.reduceRight(Cat(_,_)) }).reverse.reduceRight(Cat(_,_))