riscv/rocket-chip
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removing wires

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Huy Vo committed 2012-05-24 10:42:39 -07:00
1 parent 181b20d69c
commit 7408c9ab69
10 files changed
+42 -42
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rocket/src/main/scala/nbdcache.scala
+1 -1
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@@ -803,7 +803,7 @@ class HellaCache(co: CoherencePolicy) extends Component {
val r_req_read = r_req_load || r_req_amo
val r_req_write = r_req_store || r_req_amo
val r_req_readwrite = r_req_read || r_req_write || r_req_prefetch
val nack_hit = Wire() { Bool() }
val nack_hit = Bool()
val wb = new WritebackUnit(co)
val prober = new ProbeUnit(co)