riscv/rocket-chip
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removing wires

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This commit is contained in:
Huy Vo
2012-05-24 10:33:15 -07:00
parent 181b20d69c
commit 7408c9ab69
10 changed files with 42 additions and 42 deletions
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4
rocket/src/main/scala/icache.scala
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@ -56,8 +56,8 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten
val r_cpu_req_ppn = Reg { Bits() }
val r_cpu_req_val = Reg(resetVal = Bool(false));
val rdy = Wire() { Bool() }
val tag_hit = Wire() { Bool() }
val rdy = Bool()
val tag_hit = Bool()
when (io.cpu.req_val && rdy) {
r_cpu_req_val := Bool(true)