52 lines
1.2 KiB
Scala
52 lines
1.2 KiB
Scala
// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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class TLEdgeOut(
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client: TLClientPortParameters,
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manager: TLManagerPortParameters)
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extends TLEdgeParameters(client, manager)
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{
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// Transfers
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def Acquire(x: Int) = () // A
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def Release(x: Int) = () // C
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def ReleaseData(x: Int) = () // C
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def ProbeAck(x: Int) = () // C
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def ProbeDataAck(x: Int) = () // C
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def GrantAck(x: Int) = () // E
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// Accessors
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def Get(x: Int) = () // A
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def Put(x: Int) = () // A
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def Atomic(x: Int) = () // A
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def AccessAck(x: Int) = () // C
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def AccessDataAck(x: Int) = () // C
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def Hint(x: Int) = () // A
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def HintAck(x: Int) = () // C
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}
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class TLEdgeIn(
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client: TLClientPortParameters,
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manager: TLManagerPortParameters)
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extends TLEdgeParameters(client, manager)
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{
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// Transfers
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def Probe(x: Int) = () // B
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def Grant(x: Int) = () // D
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def GrantData(x: Int) = () // D
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def ReleaseAck(x: Int) = () // D
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// Accessors
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def Get(x: Int) = () // B
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def Put(x: Int) = () // B
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def Atomic(x: Int) = () // B
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def AccessAck(x: Int) = () // D
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def AccessDataAck(x: Int) = () // D
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def Hint(x: Int) = () // B
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def HintAck(x: Int) = () // D
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}
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